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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andrew Davis , Andrew Lunn , Heiner Kallweit , Russell King , Richard Cochran , Bjorn Andersson , Konrad Dybcio , Alexandre Torgue , Giuseppe Cavallaro , Jose Abreu , Maxime Chevallier , Maxime Coquelin , Lorenzo Bianconi Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, Mohd Ayaan Anwar X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792230324; l=2359; i=mohd.anwar@oss.qualcomm.com; s=20250907; h=from:subject:message-id; bh=LRWhJyRn3PkcxIWYRNNivl3BW306tPYAnRD6RQt/jf8=; b=8irhRRycJY4lMPeMj+cjkHGT1y1OlkmuNDgvS66f2oU8rsvggEAa5HJEeCWPbUqMEr3ZUG3Vi bxh4S3ShekxCm6dM/rJVicTZxfQe9mMakJ0qVXvyZC4RUafE1IliZuw X-Developer-Key: i=mohd.anwar@oss.qualcomm.com; a=ed25519; pk=7JNY72mz7r6hQstsamPYlUbLhQ5+W64pY4LgfSh9DJU= X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE3MDAzOCBTYWx0ZWRfX8rkVkRcXCLFl 1ZyeZ5pr8TkVTbN/Qls6Rvdh/cbRE0vRj80pmQEsqVW4AJDtNJXSnRC/H+hW/jk5iD8M8uvhvZ/ TEvre8qE8oajdMs03T/rE36FJLPF2F4= X-Proofpoint-ORIG-GUID: S9qV6XwCgOdSc-R0LMevQm_RRGMx0HMS X-Proofpoint-GUID: S9qV6XwCgOdSc-R0LMevQm_RRGMx0HMS X-Authority-Analysis: v=2.4 cv=K4O3jCWI c=1 sm=1 tr=0 ts=6ad34413 cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=zfyZ_crbsqx4_ZaO5ygA:9 a=QEXdDO2ut3YA:10 a=Kq8ClHjjuc5pcCNDwlU0:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE3MDAzOCBTYWx0ZWRfX6C4FkWhQA2Ky 0KUy1/HP4QnxpBWydLDd0NjxTjqRYVe76zD0Zkjjg9VkxzVnZi5jv35sJv0G/kkgdz2hcQ4IPpI wHmH+kuhzS1i11kVi6cPdGnCyrebubaG+vGN0QDbB2lZsA2J7iJsNtxMxJ8X7KUu/PWhKOxmVlm 2PzTbAOc1MNM/XlSPj0Dunku1RMFXXnBX6Q9coa93Ji/+5qT9lU7SebpZhIDj3yLwpCTfDEWQbr IgOCvnTieHylhdXFPmE2KxIyvjDGpoBnYQus72YsxAU3RGvUs/Tob32zqJGMeBaBbdMel7TPlQD A90umMNp8DUYwrhElhAWT/439fNYLt0X7F4LAzhXEPbNEeWBQjtwZcFPa1WX1TEajJFg2TnVpfs Fz59aVVpOtNIcWoAb2mE2107LvKov+iJm+udPXOVZZcUmR/lW8bbuNpnwoA4Bjk+m4die6Jg1ZR g4rXSO+vPWqbtK4Zcgw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-17_02,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 priorityscore=1501 phishscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610170038 Shikra integrates two Qualcomm ETHQOS controllers based on the Synopsys GMAC IP, similar to previous platforms. Register qcom,shikra-ethqos backed by a new shikra_data descriptor that enables the three NOC clocks required for DMA memory access (axi-noc, pcie-tile-axi-noc, stmmaceth), and the 36-bit DMA address width. The NOC clock rates are set using an OPP table. As part of the NOC clock voting logic, the qcom-ethqos glue driver takes a second enable reference on the "stmmaceth" clock, which is already enabled by the stmmac core. Since, all three clocks must run at 120 MHzs, managing "stmmaceth" through the same clk_bulk path keeps the rate-setting and enable/disable together. Signed-off-by: Mohd Ayaan Anwar --- drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c index 9c602755532e141f4b822721686b1481b29b7d4c..a4e083a8517d095e5571b1340f9dd4b5e0c6e81f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c @@ -307,6 +307,22 @@ static const struct ethqos_emac_driver_data emac_v4_0_0_data = { .dwmac4_addrs = ðqos_dwmac4_addrs, }; +static const char * const shikra_noc_clk_names[] = { + "stmmaceth", + "axi-noc", + "pcie-tile-axi-noc", + NULL, +}; + +static const struct ethqos_emac_driver_data shikra_data = { + .dma_addr_width = 36, + .has_emac_ge_3 = true, + .noc_clk_names = shikra_noc_clk_names, + .num_noc_clks = ARRAY_SIZE(shikra_noc_clk_names) - 1, + .rgmii_config_loopback_en = false, + .dwmac4_addrs = ðqos_dwmac4_addrs, +}; + static int ethqos_dll_configure(struct qcom_ethqos *ethqos) { struct device *dev = ðqos->pdev->dev; @@ -947,6 +963,7 @@ static const struct of_device_id qcom_ethqos_match[] = { { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data}, { .compatible = "qcom,sa8775p-ethqos", .data = &emac_v4_0_0_data}, { .compatible = "qcom,sc8280xp-ethqos", .data = &emac_v3_0_0_data}, + { .compatible = "qcom,shikra-ethqos", .data = &shikra_data}, { .compatible = "qcom,sm8150-ethqos", .data = &emac_v2_1_0_data}, { } }; -- 2.34.1