From: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
To: david@ixit.cz, andersson@kernel.org, konradybcio@kernel.org,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
bod@kernel.org, vladimir.zapolskiy@linaro.org,
loic.poulain@oss.qualcomm.com, mchehab@kernel.org
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
gjorgji.rosikopulos@oss.qualcomm.com,
jigarkumar.zala@oss.qualcomm.com,
hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com,
bryan.odonoghue@linaro.org, linux-media@vger.kernel.org,
krzysztof.kozlowski@oss.qualcomm.com, daniel@quora.org,
konrad.dybcio@oss.qualcomm.com, christopher.obbard@linaro.org,
alex.vinarskis@gmail.com
Subject: [PATCH 2/2] media: qcom: camss: account for C-PHY when calculating link frequency
Date: Fri, 16 Oct 2026 20:52:21 -0700 [thread overview]
Message-ID: <20261017035221.3816464-3-anusha.nandi@oss.qualcomm.com> (raw)
In-Reply-To: <20261017035221.3816464-1-anusha.nandi@oss.qualcomm.com>
The link-frequency divisor differs between D-PHY and C-PHY: D-PHY
carries one bit per symbol while C-PHY encodes 16 bits per 7 symbols
(~2.28 bits/symbol), as described in the MIPI CSI-2 specification.
Extend camss_get_link_freq() with a cphy parameter and scale the
per-lane divisor accordingly.
Thread the PHY type through the CSIPHY (via lane_cfg->phy_cfg) and CSID
(via a new csid_phy_config.cphy flag, populated from the linked
CSIPHY's lane configuration) call sites. The TPG path is always D-PHY.
No functional change for D-PHY: cphy is false and the divisor reduces
to the previous 2 * lanes with unscaled bpp.
Also program the CSID gen3 RX front-end's CSI2_RX_CFG0 PHY_TYPE_SEL
bit (24) from the same csid->phy.cphy flag, so C-PHY streams are
decoded as C-PHY instead of silently defaulting to D-PHY (RX counters
increment but no packets/frames are ever assembled and buf_done never
fires).
Co-developed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Anusha Arun Nandi <anusha.nandi@oss.qualcomm.com>
---
.../media/platform/qcom/camss/camss-csid-gen3.c | 2 ++
drivers/media/platform/qcom/camss/camss-csid.c | 4 +++-
drivers/media/platform/qcom/camss/camss-csid.h | 1 +
drivers/media/platform/qcom/camss/camss-csiphy.c | 8 +++++---
drivers/media/platform/qcom/camss/camss.c | 16 ++++++++++++++--
drivers/media/platform/qcom/camss/camss.h | 2 +-
6 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/media/platform/qcom/camss/camss-csid-gen3.c
index 0fdbf75fb27d..6eaeb1ba7462 100644
--- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c
+++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c
@@ -66,6 +66,7 @@
#define CSI2_RX_CFG0_VC_MODE 3
#define CSI2_RX_CFG0_DL0_INPUT_SEL 4
#define CSI2_RX_CFG0_PHY_NUM_SEL 20
+#define CSI2_RX_CFG0_PHY_TYPE_SEL 24
#define CSI2_RX_CFG0_TPG_MUX_EN BIT(27)
#define CSI2_RX_CFG0_TPG_MUX_SEL GENMASK(29, 28)
@@ -115,6 +116,7 @@ static void __csid_configure_rx(struct csid_device *csid,
camss = csid->camss;
val = (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES;
+ val |= phy->cphy << CSI2_RX_CFG0_PHY_TYPE_SEL;
val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL;
if (camss->tpg && csid->tpg_linked &&
diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c
index a00791b00feb..321bb3c86c56 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.c
+++ b/drivers/media/platform/qcom/camss/camss-csid.c
@@ -547,7 +547,7 @@ static int csid_set_clock_rates(struct csid_device *csid)
fmt = csid_get_fmt_entry(csid->res->formats->formats, csid->res->formats->nformats,
csid->fmt[MSM_CSIPHY_PAD_SINK].code);
link_freq = camss_get_link_freq(&csid->subdev.entity, fmt->bpp,
- csid->phy.lane_cnt);
+ csid->phy.lane_cnt, csid->phy.cphy);
if (link_freq < 0)
link_freq = 0;
@@ -1279,6 +1279,7 @@ static int csid_link_setup(struct media_entity *entity,
csid->phy.lane_cnt = tpg->res->lane_cnt;
csid->phy.csiphy_id = tpg->id;
csid->phy.lane_assign = csid_get_lane_assign(NULL, csid->phy.lane_cnt);
+ csid->phy.cphy = false;
csid->tpg_linked = true;
} else {
csiphy = v4l2_get_subdevdata(sd);
@@ -1293,6 +1294,7 @@ static int csid_link_setup(struct media_entity *entity,
lane_cfg = &csiphy->cfg.csi2->lane_cfg;
csid->phy.lane_cnt = lane_cfg->num_data;
csid->phy.lane_assign = csid_get_lane_assign(lane_cfg, lane_cfg->num_data);
+ csid->phy.cphy = (lane_cfg->phy_cfg == V4L2_MBUS_CSI2_CPHY);
csid->tpg_linked = false;
}
}
diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h
index 5296b10f6bac..00e2669db64c 100644
--- a/drivers/media/platform/qcom/camss/camss-csid.h
+++ b/drivers/media/platform/qcom/camss/camss-csid.h
@@ -70,6 +70,7 @@ struct csid_phy_config {
u32 lane_assign;
u32 en_vc;
u8 need_vc_update;
+ bool cphy;
};
struct csid_device;
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c
index f99eea2ef228..60d58becc7c5 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy.c
@@ -146,8 +146,9 @@ static int csiphy_set_clock_rates_legacy(struct csiphy_device *csiphy)
u8 bpp = csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->formats->nformats,
csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data;
+ const bool cphy = (csiphy->cfg.csi2->lane_cfg.phy_cfg == V4L2_MBUS_CSI2_CPHY);
- link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes);
+ link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes, cphy);
if (link_freq < 0)
link_freq = 0;
@@ -272,9 +273,10 @@ static int csiphy_stream_on_legacy(struct csiphy_device *csiphy)
u8 bpp = csiphy_get_bpp(csiphy->res->formats->formats, csiphy->res->formats->nformats,
csiphy->fmt[MSM_CSIPHY_PAD_SINK].code);
u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data;
+ const bool cphy = (csiphy->cfg.csi2->lane_cfg.phy_cfg == V4L2_MBUS_CSI2_CPHY);
u8 val;
- link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes);
+ link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes, cphy);
if (link_freq < 0) {
dev_err(csiphy->camss->dev,
@@ -336,7 +338,7 @@ static int csiphy_stream_on(struct csiphy_device *csiphy)
dphy_cfg = &dphy_opts.mipi_dphy;
- link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes);
+ link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes, false);
if (link_freq <= 0) {
dev_err(dev,
diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index c888e78256b3..d525358afa04 100644
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -32,6 +32,15 @@
#define CAMSS_CLOCK_MARGIN_NUMERATOR 105
#define CAMSS_CLOCK_MARGIN_DENOMINATOR 100
+/*
+ * C-PHY encodes data at 16/7 ~ 2.28 bits/symbol, whereas D-PHY does not encode
+ * data (16/16 = 1 bit/symbol). Scale the per-lane divisor accordingly when
+ * deriving the link frequency from the sensor pixel rate.
+ */
+#define CAMSS_COMMON_PHY_DIVIDENT 16
+#define CAMSS_CPHY_DIVISOR 7
+#define CAMSS_DPHY_DIVISOR 16
+
static const struct parent_dev_ops vfe_parent_dev_ops;
static const struct camss_subdev_resources csiphy_res_8x16[] = {
@@ -4624,19 +4633,22 @@ struct media_pad *camss_find_sensor_pad(struct media_entity *entity)
* @entity: Media entity in the current pipeline
* @bpp: Number of bits per pixel for the current format
* @lanes: Number of lanes in the link to the sensor
+ * @cphy: True if C-PHY encoding is used
*
* Return link frequency on success or a negative error code otherwise
*/
s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp,
- unsigned int lanes)
+ unsigned int lanes, const bool cphy)
{
struct media_pad *sensor_pad;
+ unsigned int div = lanes * 2 * (cphy ? CAMSS_CPHY_DIVISOR :
+ CAMSS_DPHY_DIVISOR);
sensor_pad = camss_find_sensor_pad(entity);
if (!sensor_pad)
return -ENODEV;
- return v4l2_get_link_freq(sensor_pad, bpp, 2 * lanes);
+ return v4l2_get_link_freq(sensor_pad, CAMSS_COMMON_PHY_DIVIDENT * bpp, div);
}
/*
diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index ba3d51d9c0bf..f7ee2ae792c9 100644
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -170,7 +170,7 @@ int camss_enable_clocks(int nclocks, struct camss_clock *clock,
void camss_disable_clocks(int nclocks, struct camss_clock *clock);
struct media_pad *camss_find_sensor_pad(struct media_entity *entity);
s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp,
- unsigned int lanes);
+ unsigned int lanes, const bool cphy);
int camss_get_pixel_clock(struct media_entity *entity, u64 *pixel_clock);
int camss_pm_domain_on(struct camss *camss, int id);
void camss_pm_domain_off(struct camss *camss, int id);
--
2.34.1
next prev parent reply other threads:[~2026-10-17 3:52 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-17 3:52 [PATCH 0/2] media: qcom: camss: track PHY type and scale link frequency for C-PHY Anusha Arun Nandi
2026-10-17 3:52 ` [PATCH 1/2] media: qcom: camss: csiphy: record PHY type from device-tree bus-type Anusha Arun Nandi
2026-10-17 3:52 ` Anusha Arun Nandi [this message]
2026-10-17 10:12 ` [PATCH 2/2] media: qcom: camss: account for C-PHY when calculating link frequency George Neacsu
2026-10-17 17:30 ` [PATCH 0/2] media: qcom: camss: track PHY type and scale link frequency for C-PHY Nihal Kumar Gupta
2026-10-17 17:35 ` Krzysztof Kozlowski
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