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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-360820a79c7sm10867636eec.18.2026.10.16.21.17.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Oct 2026 21:17:34 -0700 (PDT) From: Anusha Arun Nandi To: david@ixit.cz, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, bod@kernel.org, vladimir.zapolskiy@linaro.org, loic.poulain@oss.qualcomm.com, mchehab@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, gjorgji.rosikopulos@oss.qualcomm.com, jigarkumar.zala@oss.qualcomm.com, hariram.purushothaman@oss.qualcomm.com, akapatra@quicinc.com, bryan.odonoghue@linaro.org, linux-media@vger.kernel.org, krzysztof.kozlowski@oss.qualcomm.com, daniel@quora.org, konrad.dybcio@oss.qualcomm.com, christopher.obbard@linaro.org, alex.vinarskis@gmail.com Subject: [PATCH 0/3] phy: core, qcom-mipi-csi2: add generic MIPI C-PHY support Date: Fri, 16 Oct 2026 21:17:30 -0700 Message-Id: <20261017041733.3946816-1-anusha.nandi@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: Doo-KCODTGYpSExCa5G_EalJcvtQH6K_ X-Proofpoint-ORIG-GUID: Doo-KCODTGYpSExCa5G_EalJcvtQH6K_ X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE3MDAxNiBTYWx0ZWRfX+5w6VKDA8Y4D 9VOSlYEB8VTeK3Lla0T4HAqpNEla1S6cjIf2RcVRiZfhV9Kiy21fjjGDlAjGJFfdwxfbdMAxxYZ dWxUmoNtf1QR9KIwekMObsXB0uoU7VI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE3MDAxNiBTYWx0ZWRfX0vGh8zV61iPO HnE7CdZUGnmLwcBAF3EjG//l2JZVFEojqnQcfv9pd0PYXDfGb3wyv9aE65Z/yNYnT5tjNYyM03Y 946UcX5dRvqJ9qrJU/yVdm0+g6B46aiXB+NKfBK11cLELiWipQcOyjy3Ng3EJYF9fXhrbS5PPpy b0kFoiWn4t/yEmLikeyuvZObX5MQdpMrrmqJSowMGppgBMbMHPUkuHPNhxl9dI1/7OOn0fP4YpB OcmGUWUwJJD9aTI3bz4hHeZmNz/QskyLvJQaBI9S48ivttGoAR6yQk4s+NYS75w9gqBn4kKhcDK tONo84I43O3SdnGXCx6oMpaD5eR564qi4fxhA1KWwWLIMhpTfNGfvft4UlXRqSbq6A4IiikWUGa d3Tp+Kdf1zRY9bVgGPsgKVou6LplaCp+jWsBKyZ/+p1y9PBPl18h0sNy8Fv7WRO1fshwmQbLcHO ZRzU9VdGfQSt3IUu9Aw== X-Authority-Analysis: v=2.4 cv=SKzXx+vH c=1 sm=1 tr=0 ts=6ad2f6e1 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=UyFj12KqJ2bFa5q0Gy0A:9 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-17_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 impostorscore=0 spamscore=0 suspectscore=0 phishscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610170016 This series adds C-PHY (3-phase) support to the generic PHY framework and to the Qualcomm MIPI CSI2 PHY driver, mirroring the existing MIPI D-PHY generic configuration API. Patch 1 adds the core API: PHY_MODE_MIPI_CPHY, struct phy_configure_opts_mipi_cphy, and the phy_mipi_cphy_get_default_config()/_for_hsclk()/config_validate() helpers, following the MIPI Alliance C-PHY v1.0 timing spec. It has no functional effect on its own, since no provider selects GENERIC_PHY_MIPI_CPHY yet. Patch 2 wires C-PHY mode into the qcom-mipi-csi2 driver for SA8775P: the PHY mode is now derived from the devicetree endpoint's bus-type property at probe time (D-PHY by default, C-PHY if MEDIA_BUS_TYPE_CSI2_CPHY), phy_qcom_mipi_csi2_set_mode() validates a consumer's phy_set_mode() call against that DT-derived mode, and the configure/power_on/power_off/lanes_enable/lanes_disable paths dispatch to the new C-PHY 3-phase hw ops accordingly. Patch 3 extends the same C-PHY mode selection to SC7280, porting the legacy in-tree driver's SM8250/SC7280 C-PHY lane-register sequence. No dt-bindings changes are needed for either SoC: the existing qcom,sa8775p-csi2-phy / qcom,sc7280-csi2-phy schemas already document both D-PHY and C-PHY bus-type values. Depends-on: https://lore.kernel.org/all/20261017040529.3832120-1-anusha.nandi@oss.qualcomm.com/ Jigarkumar Zala (3): phy: core: add generic MIPI C-PHY configuration API phy: qcom-mipi-csi2: Add sa8775p C-PHY support phy: qcom-mipi-csi2: Add sc7280 C-PHY support Anusha Arun Nandi (3): phy: core: add generic MIPI C-PHY configuration API phy: qcom-mipi-csi2: Add sa8775p C-PHY support phy: qcom-mipi-csi2: Add sc7280 C-PHY support drivers/phy/Kconfig | 9 + drivers/phy/Makefile | 1 + drivers/phy/phy-core-mipi-cphy.c | 129 ++++ drivers/phy/qualcomm/Kconfig | 1 + drivers/phy/qualcomm/Makefile | 3 +- .../qualcomm/phy-qcom-mipi-csi2-3ph-cphy.c | 561 ++++++++++++++++++ .../qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 8 +- .../phy/qualcomm/phy-qcom-mipi-csi2-core.c | 133 ++++- drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 31 + include/linux/phy/phy-mipi-cphy.h | 177 ++++++ include/linux/phy/phy.h | 5 + 11 files changed, 1029 insertions(+), 29 deletions(-) create mode 100644 drivers/phy/phy-core-mipi-cphy.c create mode 100644 drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-cphy.c create mode 100644 include/linux/phy/phy-mipi-cphy.h Best regards, -- Anusha Arun Nandi -- 2.34.1