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[180.177.138.120]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-360820a02b8sm17766277eec.17.2026.10.17.07.08.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 17 Oct 2026 07:08:09 -0700 (PDT) From: Hung-Chun Tseng To: Philipp Zabel , Guodong Xu , Yixun Lan Cc: Troy Mitchell , Alex Elder , linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH] reset: spacemit: Fix the RCPU2 PWM reset registers Date: Sat, 17 Oct 2026 22:08:05 +0800 Message-ID: <20261017140805.3278709-1-alan.tseng.cs@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Every entry in k1_rcpu2_resets[] uses RCPU2_PWM9_CLK_RST, so asserting or deasserting the reset of any RCPU2 PWM from 0 to 8 acts on PWM9 instead. Each PWM has its own register, RCPU2_PWMn_CLK_RST at offset 4 * n, as k1-syscon.h already defines. On a Milk-V Jupiter running the vendor kernel, which uses RCPU2 PWM2 for the fan, the RCPU2 registers read: 0x00: 0x4 0x04: 0x4 0x08: 0x1 0x0c: 0x4 ... 0x24: 0x4 Only PWM2's register has its reset deasserted, which matches one register per PWM. Use the matching register for each reset. No in-tree device tree uses the RCPU2 PWMs yet, so this has no effect on current boards, but it would break the first one that does. Build-tested only (riscv defconfig, W=1); the fix could not be tested at runtime, as mainline has no RCPU2 PWM node to exercise it. Fixes: c479d7cf06c3 ("reset: spacemit: add support for SpacemiT CCU resets") Assisted-by: claude-opus-5-5 Signed-off-by: Hung-Chun Tseng --- drivers/reset/spacemit/reset-spacemit-k1.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/reset/spacemit/reset-spacemit-k1.c b/drivers/reset/spacemit/reset-spacemit-k1.c index 8f3b5329e..dbd783c13 100644 --- a/drivers/reset/spacemit/reset-spacemit-k1.c +++ b/drivers/reset/spacemit/reset-spacemit-k1.c @@ -154,15 +154,15 @@ static const struct ccu_reset_controller_data k1_rcpu_reset_data = { }; static const struct ccu_reset_data k1_rcpu2_resets[] = { - [RESET_RCPU2_PWM0] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), - [RESET_RCPU2_PWM1] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), - [RESET_RCPU2_PWM2] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), - [RESET_RCPU2_PWM3] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), - [RESET_RCPU2_PWM4] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), - [RESET_RCPU2_PWM5] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), - [RESET_RCPU2_PWM6] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), - [RESET_RCPU2_PWM7] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), - [RESET_RCPU2_PWM8] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM0] = RESET_DATA(RCPU2_PWM0_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM1] = RESET_DATA(RCPU2_PWM1_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM2] = RESET_DATA(RCPU2_PWM2_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM3] = RESET_DATA(RCPU2_PWM3_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM4] = RESET_DATA(RCPU2_PWM4_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM5] = RESET_DATA(RCPU2_PWM5_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM6] = RESET_DATA(RCPU2_PWM6_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM7] = RESET_DATA(RCPU2_PWM7_CLK_RST, BIT(2), BIT(0)), + [RESET_RCPU2_PWM8] = RESET_DATA(RCPU2_PWM8_CLK_RST, BIT(2), BIT(0)), [RESET_RCPU2_PWM9] = RESET_DATA(RCPU2_PWM9_CLK_RST, BIT(2), BIT(0)), }; -- 2.43.0