From: Yazen Ghannam <yazen.ghannam@amd.com>
To: Lin Wang <wanglin@open-hieco.net>
Cc: Borislav Petkov <bp@alien8.de>,
Mario Limonciello <mario.limonciello@amd.com>,
Pu Wen <puwen@hygon.cn>, Thomas Gleixner <tglx@kernel.org>,
Ingo Molnar <mingo@redhat.com>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>, Tony Luck <tony.luck@intel.com>,
x86@kernel.org, linux-edac@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 1/7] x86/hygon: Add Family 0x18 DF node enumeration
Date: Sat, 17 Oct 2026 10:52:26 -0400 [thread overview]
Message-ID: <20261017145226.GA359037@yaz-khff2.amd.com> (raw)
In-Reply-To: <20261009090111.151878-2-wanglin@open-hieco.net>
On Fri, Oct 09, 2026 at 05:01:05PM +0800, Lin Wang wrote:
> The AMD node code locates function 3 for node N at PCI slot 0x18 + N.
> Hygon has no equivalent node-index-to-slot mapping: DF F3 devices are
> discovered by PCI ID and the PCI BDF is only an access point.
>
> Add a Hygon node cache that enumerates DF devices by PCI ID and obtains
> the socket ID and DFID for each node from DF configuration registers.
> Validate the enumerated socket set against the hardware-reported socket
> mask before making the cache available.
>
> Place Core and DDR Dies (CDDs) before I/O Dies (IODs) and order each
> group by socket and DFID to provide dense node indices. Export
> interfaces for node counts and identity, F3/F4 lookup, and PCI
> device-to-node lookup.
>
> Signed-off-by: Lin Wang <wanglin@open-hieco.net>
> ---
> MAINTAINERS | 3 +
> arch/x86/Kconfig | 4 +
> arch/x86/include/asm/hygon/node.h | 128 +++++++
> arch/x86/kernel/Makefile | 1 +
> arch/x86/kernel/hygon_node.c | 601 ++++++++++++++++++++++++++++++
> 5 files changed, 737 insertions(+)
> create mode 100644 arch/x86/include/asm/hygon/node.h
> create mode 100644 arch/x86/kernel/hygon_node.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index f53047aa8d3c..1c5be275a28a 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -12137,9 +12137,12 @@ F: drivers/input/touchscreen/hycon-hy46xx.c
>
> HYGON PROCESSOR SUPPORT
> M: Pu Wen <puwen@hygon.cn>
> +M: Lin Wang <wanglin@open-hieco.net>
Any feedback from Pu Wen?
> L: linux-kernel@vger.kernel.org
> S: Maintained
> +F: arch/x86/include/asm/hygon/
> F: arch/x86/kernel/cpu/hygon.c
> +F: arch/x86/kernel/hygon_node.c
>
[...]
> +
> +u16 hygon_node_num(void)
> +{
> + return df_cache.num_nodes;
> +}
> +EXPORT_SYMBOL_GPL(hygon_node_num);
> +
> +u16 hygon_cdd_num(void)
> +{
> + return df_cache.num_cdd;
> +}
> +EXPORT_SYMBOL_GPL(hygon_cdd_num);
> +
> +int hygon_node_get_info(u16 node, struct hygon_node_info *info)
> +{
> + const struct df_node *n;
> +
> + if (!info)
> + return -EINVAL;
> +
> + if (!df_cache.nodes)
> + return -ENODEV;
> +
> + if (node >= df_cache.num_nodes)
> + return -EINVAL;
> +
> + n = &df_cache.nodes[node];
> + info->socket_id = n->socket_id;
> + info->dfid = n->dfid;
> + info->type = n->is_cdd ? HYGON_NODE_CDD : HYGON_NODE_IOD;
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(hygon_node_get_info);
> +
> +struct pci_dev *hygon_node_get_func(u16 node, u8 func)
> +{
> + if (!df_cache.nodes)
> + return NULL;
> +
> + if (node >= df_cache.num_nodes)
> + return NULL;
> +
> + switch (func) {
> + case HYGON_DF_F3:
> + return pci_dev_get(df_cache.nodes[node].misc);
> + case HYGON_DF_F4:
> + return pci_dev_get(df_cache.nodes[node].link);
> + default:
> + return NULL;
> + }
> +}
> +EXPORT_SYMBOL_GPL(hygon_node_get_func);
> +
> +int hygon_pci_dev_to_df_node(struct pci_dev *pdev)
> +{
> + u16 i;
> +
> + if (!pdev)
> + return -EINVAL;
> +
> + if (!df_cache.nodes)
> + return -ENODEV;
> +
> + for (i = 0; i < df_cache.num_nodes; i++) {
> + struct pci_dev *misc = df_cache.nodes[i].misc;
> +
> + if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) &&
> + misc->bus->number == pdev->bus->number &&
> + PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn))
> + return i;
> + }
> +
> + return -ENODEV;
> +}
> +EXPORT_SYMBOL_GPL(hygon_pci_dev_to_df_node);
> +
These exported functions don't have any callers in this set.
This issue was mentioned in the last revision for a different function.
But the guidance should be followed in general.
> +static int __init df_node_init(void)
> +{
> + int ret;
> +
> + if (!get_df_cfg())
> + return 0;
> +
> + ret = build_cache();
> + if (ret) {
> + pr_warn("DF node cache build failed: %d\n", ret);
> + return ret;
> + }
> +
Have you considered cases where the cache build fails but that are
expected?
We've had similar issues recently like this related to virtualization.
In summary: this failure is a true issue on bare metal, so the user
should be warned. But the failure is expected within a guest VM.
Thanks,
Yazen
next prev parent reply other threads:[~2026-10-17 14:52 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-09 9:01 [PATCH v7 0/7] x86/hygon: Add Family 0x18 DF node enumeration and SMN access Lin Wang
2026-10-09 9:01 ` [PATCH v7 1/7] x86/hygon: Add Family 0x18 DF node enumeration Lin Wang
2026-10-17 14:52 ` Yazen Ghannam [this message]
2026-10-09 9:01 ` [PATCH v7 2/7] x86/hygon: Map CPU NodeIds to DF nodes Lin Wang
2026-10-17 15:10 ` Yazen Ghannam
2026-10-09 9:01 ` [PATCH v7 3/7] EDAC/amd64: Stop matching Hygon CPUs Lin Wang
2026-10-17 15:16 ` Yazen Ghannam
2026-10-09 9:01 ` [PATCH v7 4/7] RAS/AMD/ATL: Match AMD CPUs only Lin Wang
2026-10-17 15:20 ` Yazen Ghannam
2026-10-09 9:01 ` [PATCH v7 5/7] x86/amd_nb: Restrict the northbridge framework to AMD CPUs Lin Wang
2026-10-09 9:01 ` [PATCH v7 6/7] x86/amd_node: Restrict SMN setup " Lin Wang
2026-10-17 15:33 ` Yazen Ghannam
2026-10-09 9:01 ` [PATCH v7 7/7] x86/hygon: Add Family 0x18 SMN access Lin Wang
2026-10-17 15:41 ` Yazen Ghannam
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