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Mon, 19 Oct 2026 02:25:25 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1831c4d4675sm26682584c88.21.2026.10.19.02.25.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2026 02:25:25 -0700 (PDT) From: Krishna Chaitanya Chundru Subject: [PATCH v2 0/6] PCI: qcom-ep: Add PCIe Endpoint support for Monaco Date: Mon, 19 Oct 2026 14:55:08 +0530 Message-Id: <20261019-monaco_ep-v2-0-852cb9f5d012@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAPTh1WoC/02Nyw6CMBBFf4XM2pK2PoKu/A9DTDtMpUYodoBoC P9uQRdubnKSk3MnYIqeGE7ZBJFGzz60CfQmA6xNeyPhq8SgpT7IoypEE1qD4UqdcFbtnHGVJER IfhfJ+dfaupRf5sHeCfslsBi15z7E93o2qsX7dbX6645KSHHY4l4X2llZ2XNgzp+DeWBomjwNl PM8fwC7j2WOuwAAAA== X-Change-ID: 20260918-monaco_ep-fb14fafd0ecc To: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Krishna Chaitanya Chundru , Krzysztof Kozlowski , Manivannan Sadhasivam , Konrad Dybcio X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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Signed-off-by: Krishna Chaitanya Chundru --- Changes in v2: - dt-bindings: PCI: qcom-ep: Drop qcs8300 compatible from the standalone enum list(Krzysztof) - PCI: qcom-ep: Fix qcom_pcie_disable_resources() to tear down resources in strict LIFO order (phy -> clocks -> interconnect bandwidth), matching the enable path's error-unwind sequence. (Sashiko AI review) - arm64: qcom: monaco: Add reset-gpios and wake-gpios to the pcie0_ep and pcie1_ep nodes so the EP driver owns and correctly manages the PERST# and WAKE# lines; drop the output-low override from the wake-pins pinctrl state that was permanently asserting WAKE#. (Sashiko AI review) - phy: qcom: qmp-pcie: Reword commit message to clarify the new RX tuning sequence for the 16 GT/s x4 PHY is common to RC and EP modes, not EP-only. - Link to v1: https://patch.msgid.link/20260921-monaco_ep-v1-0-63c5282fb0db@oss.qualcomm.com --- Krishna Chaitanya Chundru (6): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add qcs8300 16 GT/s PHY dt-bindings: PCI: qcom-ep: Add QCS8300 compatible phy: qcom: qmp-pcie: Add endpoint PHY configuration for QCS8300 PCI: qcom-ep: Set initial interconnect bandwidth before enabling clocks arm64: qcom: monaco: Fix pcie1_phy compatible to list qcs8300 first arm64: qcom: monaco: Add PCIe Endpoint nodes .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 4 + .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 87 ++++++------ arch/arm64/boot/dts/qcom/monaco.dtsi | 150 ++++++++++++++++++++- drivers/pci/controller/dwc/pcie-qcom-ep.c | 36 ++--- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 105 +++++++++++++++ 5 files changed, 322 insertions(+), 60 deletions(-) --- base-commit: 0927a1e73df63eda38bb120b91e50d746d640e17 change-id: 20260918-monaco_ep-fb14fafd0ecc Best regards, -- Krishna Chaitanya Chundru