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Describe the Endpoint nodes for both controllers, including their register regions, clocks, interrupts, interconnects, IOMMU mappings, resets, power domains, and PHY connections etc. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/monaco.dtsi | 147 +++++++++++++++++++++++++++++++++++ 1 file changed, 147 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index d7d135e87a8c..12cd7d5f37a3 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -2405,6 +2406,57 @@ pcieport0: pcie@0 { }; }; + pcie0_ep: pcie-ep@1c00000 { + compatible = "qcom,qcs8300-pcie-ep", "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40200000 0x0 0x1fe00000>, + <0x0 0x01c03000 0x0 0x1000>, + <0x0 0x40005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = , + , + ; + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus = <&pcie_smmu 0x0000 0x7f>; + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "core"; + power-domains = <&gcc GCC_PCIE_0_GDSC>; + phys = <&pcie0_phy>; + phy-names = "pciephy"; + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie0_ep_default_state>; + pinctrl-names = "default"; + num-lanes = <2>; + linux,pci-domain = <0>; + + status = "disabled"; + }; + pcie0_phy: phy@1c04000 { compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy"; reg = <0x0 0x01c04000 0x0 0x2000>; @@ -2596,6 +2648,57 @@ pcieport1: pcie@0 { }; }; + pcie1_ep: pcie-ep@1c10000 { + compatible = "qcom,qcs8300-pcie-ep", "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c10000 0x0 0x3000>, + <0x0 0x60000000 0x0 0xf20>, + <0x0 0x60000f20 0x0 0xa8>, + <0x0 0x60001000 0x0 0x4000>, + <0x0 0x60200000 0x0 0x1fe00000>, + <0x0 0x01c13000 0x0 0x1000>, + <0x0 0x60005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = , + , + ; + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + dma-coherent; + iommus = <&pcie_smmu 0x0080 0x7f>; + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "core"; + power-domains = <&gcc GCC_PCIE_1_GDSC>; + phys = <&pcie1_phy>; + phy-names = "pciephy"; + reset-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 21 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pcie1_ep_default_state>; + pinctrl-names = "default"; + num-lanes = <4>; + linux,pci-domain = <1>; + + status = "disabled"; + }; + pcie1_phy: phy@1c14000 { compatible = "qcom,qcs8300-qmp-gen4x4-pcie-phy", "qcom,sa8775p-qmp-gen4x4-pcie-phy"; @@ -6225,6 +6328,50 @@ tlmm: pinctrl@f100000 { #interrupt-cells = <2>; wakeup-parent = <&pdc>; + pcie0_ep_default_state: pcie0-ep-default-state { + wake-pins { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + }; + + clkreq-pins { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio2"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + + pcie1_ep_default_state: pcie1-ep-default-state { + wake-pins { + pins = "gpio21"; + function = "gpio"; + drive-strength = <2>; + }; + + clkreq-pins { + pins = "gpio22"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-pins { + pins = "gpio23"; + function = "gpio"; + input-enable; + bias-pull-up; + }; + }; + cam0_default: cam0-default-state { pins = "gpio67"; function = "cam_mclk"; -- 2.34.1