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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3607ee0cab0sm33841550eec.3.2026.10.18.19.15.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Oct 2026 19:15:50 -0700 (PDT) From: Peter Chen To: Bjorn Andersson , Konrad Dybcio Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , Abel Vesa , Wesley Cheng , Udipto Goswami , Jack Pham , Pratham Pratap , Krishna Kurapati , Thinh Nguyen , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Chen Subject: [PATCH v2 0/4] arm64: dts: qcom: Set snps,resume-hs-terminations for M31 eUSB2 PHY platforms Date: Sun, 18 Oct 2026 19:15:43 -0700 Message-ID: <20261019021547.1694088-1-peter.chen@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDE5MDAwOCBTYWx0ZWRfX4EDHHyB+XDTf nwMrULxn4lVOWBk2CqtapvrZSqZYge5N4uTUa1loT5P20zlidmzFcwjOHbky/1Jn3GsXxpMfFBJ Lo3LAiuBL+HSVgC1yfEK+Jlr11QOfdk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDE5MDAwOCBTYWx0ZWRfX+YtEtq8Yw1Bj kwiKKbAy+/QG5pYHTuaa1xlm1pSVCiN8yDgHdAEpkvGZ3a72w/zAE1v2i2He+YN6MvDr8TTKwmW yYn0qVULnpuD3iW4KGOaZ71fB7MYE8S5ZZBpiWMKDMJmp/ClpGmNo9fM/hz67xuGZRsCbtsKYEL ffRzDiIMLFggR1htGxLhp+biICA7NFvmTT7ZKRnjxvhvByQchUsEOFM08/9srfsZ4zTAgbDrcJl jpAZMTEFxO3jvNQraE1FJ247u09BMIjUQ8trSz9pgFVrmpe3K2QmcB07pG2vqjT/013GE4J3i6/ wJmgTUcda/hDPjl4fChUd0v7tmTBkb593pYMXLPYABvnVrtD7NPzuqO50gxcKDV2+xDXaDugD5N m6IEHT9OhETzz4fiP0CY8WlyfCCGWSTdgiSDOWsl1lodo9pPofcg85Wqj7RfX8lMSgWzb7mKza+ l44ozc+fMbY/qo+ydZA== X-Proofpoint-ORIG-GUID: hOsXR_qiVhp3MGadg1GF7s5owASbBBDq X-Proofpoint-GUID: hOsXR_qiVhp3MGadg1GF7s5owASbBBDq X-Authority-Analysis: v=2.4 cv=CP6/zhrD c=1 sm=1 tr=0 ts=6ad57d58 cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=7Cx1X0J1WT0CMOh0E7cA:9 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-19_01,2026-10-14_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 impostorscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610190008 The DWC3 controllers on Qualcomm SoCs paired with the M31 eUSB2 PHY need GUCTL1[10] (RESUME_OPMODE_HS_HOST) set for host-mode USB2 L2/L1 resume, as required by the HPG. Without it, a USB2 HS device cannot be reset after it is runtime resumed: PORTSC.PR never clears (PORTSC = 0xe11) and the hub driver fails with "port_wait_reset: err = -16". Set snps,resume-hs-terminations, which makes dwc3 core set GUCTL1[10], on all platforms using the M31 eUSB2 PHY: Glymur, SM8750, Kaanapali and Hawi. Changes in v2: - Apply the same fix to SM8750, Kaanapali and Hawi, which also use the M31 eUSB2 PHY (Konrad) - Collect Reviewed-by tag from Konrad for the Glymur patch v1: https://lore.kernel.org/all/20261016091336.2715717-1-peter.chen@oss.qualcomm.com/ Peter Chen (4): arm64: dts: qcom: glymur: Set snps,resume-hs-terminations for USB controllers arm64: dts: qcom: sm8750: Set snps,resume-hs-terminations for USB controller arm64: dts: qcom: kaanapali: Set snps,resume-hs-terminations for USB controller arm64: dts: qcom: hawi: Set snps,resume-hs-terminations for USB controller arch/arm64/boot/dts/qcom/glymur.dtsi | 5 +++++ arch/arm64/boot/dts/qcom/hawi.dtsi | 1 + arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1 + arch/arm64/boot/dts/qcom/sm8750.dtsi | 1 + 4 files changed, 8 insertions(+) -- 2.43.0