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Sun, 18 Oct 2026 20:49:19 -0700 (PDT) Received: from center.jhjvjihww5qejoy14qwv1cc4td.frax.internal.cloudapp.net ([131.189.143.225]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1bd9b8b5fsm371302795e9.9.2026.10.18.20.49.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Oct 2026 20:49:18 -0700 (PDT) From: Orgad Shaneh To: tsbogend@alpha.franken.de Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] MIPS: OCTEON: program L2C_CTL on CNF71XX too Date: Mon, 19 Oct 2026 03:49:18 +0000 Message-ID: <20261019034918.3805764-1-orgads@gmail.com> X-Mailer: git-send-email 2.47.3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Since commit bd978130307c ("MIPS: OCTEON: program L2C_CTL, not L2C_CFG, on OCTEON II"), cvmx_helper_initialize_packet_io_global() writes L2C_CTL instead of L2C_CFG, because L2C_CFG does not exist on OCTEON II and writing it hangs a CN6335. The test is OCTEON_CN6XXX, which leaves the CNF71XX - also an OCTEON II, as OCTEON_IS_OCTEON2() and the rest of this file treat it - writing the register that commit says is not there. Use OCTEON_IS_OCTEON2(). OCTEON III (CN7XXX) still takes the L2C_CFG path, as before: I have no such part and do not know which register it wants. Fixes: bd978130307c ("MIPS: OCTEON: program L2C_CTL, not L2C_CFG, on OCTEON II") Assisted-by: LLM Signed-off-by: Orgad Shaneh --- Found by the Sashiko review bot on the original series. By inspection only: I have no CNF71XX board to test on. The Fixes: hash is the one in mips-next. diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper.c b/arch/mips/cavium-octeon/executive/cvmx-helper.c index 107b1be..c02448b 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper.c @@ -1028,7 +1028,7 @@ int cvmx_helper_initialize_packet_io_global(void) * to the cores. This avoids conditions where IO blocks might * be starved under very high L2 loads. */ - if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + if (OCTEON_IS_OCTEON2()) { union cvmx_l2c_ctl l2c_ctl; l2c_ctl.u64 = cvmx_read_csr(CVMX_L2C_CTL);