[PATCH v7 07/14] PCI: rzg3s-host: Use cached MSI address in .irq_compose_msi_msg()

[Claudiu Beznea <claudiu.beznea@kernel.org>]

From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

The MSI window address is already cached in msi->window_base when the
MSI window is configured. Use it to fill msg->address_lo and
msg->address_hi in .irq_compose_msi_msg() instead of reading it back
from the controller registers.

This avoids unnecessary register accesses.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
---

Changes in v7:
- none, this patch is new

 drivers/pci/controller/pcie-rzg3s-host.c | 14 ++------------
 1 file changed, 2 insertions(+), 12 deletions(-)

diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
index b0a150262959..6acb0231a067 100644
--- a/drivers/pci/controller/pcie-rzg3s-host.c
+++ b/drivers/pci/controller/pcie-rzg3s-host.c
@@ -660,19 +660,9 @@ static void rzg3s_pcie_irq_compose_msi_msg(struct irq_data *data,
 					   struct msi_msg *msg)
 {
 	struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(data);
-	struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi);
-	u32 lo, hi;
-
-	/*
-	 * Enable and msg data enable bits are part of the address lo. Drop
-	 * them along with the unused bit.
-	 */
-	lo = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRL) &
-	     RZG3S_PCI_MSIRCVWADRL_MASK;
-	hi = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRU);
 
-	msg->address_lo = lo;
-	msg->address_hi = hi;
+	msg->address_lo = lower_32_bits(msi->window_base);
+	msg->address_hi = upper_32_bits(msi->window_base);
 	msg->data = data->hwirq;
 }
 
-- 
2.43.0