From: Jiale Yao <yaojiale02@163.com>
To: Mark Brown <broonie@kernel.org>,
Atsushi Nemoto <atsushi.nemoto@sord.co.jp>,
linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Jiale Yao <yaojiale02@163.com>
Subject: [PATCH 2/2] spi: ti-qspi: handle setup clock runtime resume failure
Date: Mon, 19 Oct 2026 16:44:43 +0800 [thread overview]
Message-ID: <20261019084443.1824122-3-yaojiale02@163.com> (raw)
In-Reply-To: <20261019084443.1824122-1-yaojiale02@163.com>
ti_qspi_setup_clk() writes controller registers after an unchecked
pm_runtime_resume_and_get() call. Runtime resume can fail, leaving the
controller unavailable while the helper continues with the register
access and later drops a reference that was not acquired.
Return the runtime resume error from the helper and propagate it through
the memory-map and transfer paths before any clock register access.
Fixes: 8d0b512844fd ("spi: spi-ti-qspi: Support per-transfer and per-slave speed_hz settings")
Signed-off-by: Jiale Yao <yaojiale02@163.com>
---
drivers/spi/spi-ti-qspi.c | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-ti-qspi.c b/drivers/spi/spi-ti-qspi.c
index 34b154922ff2..5851574a4292 100644
--- a/drivers/spi/spi-ti-qspi.c
+++ b/drivers/spi/spi-ti-qspi.c
@@ -167,10 +167,10 @@ static int ti_qspi_setup(struct spi_device *spi)
return 0;
}
-static void ti_qspi_setup_clk(struct ti_qspi *qspi, u32 speed_hz)
+static int ti_qspi_setup_clk(struct ti_qspi *qspi, u32 speed_hz)
{
struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
- int clk_div;
+ int clk_div, ret;
u32 clk_ctrl_reg, clk_rate, clk_ctrl_new;
clk_rate = clk_get_rate(qspi->fclk);
@@ -178,7 +178,9 @@ static void ti_qspi_setup_clk(struct ti_qspi *qspi, u32 speed_hz)
clk_div = clamp(clk_div, 0, QSPI_CLK_DIV_MAX);
dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", speed_hz, clk_div);
- pm_runtime_resume_and_get(qspi->dev);
+ ret = pm_runtime_resume_and_get(qspi->dev);
+ if (ret < 0)
+ return ret;
clk_ctrl_new = QSPI_CLK_EN | clk_div;
if (ctx_reg->clkctrl != clk_ctrl_new) {
@@ -195,6 +197,8 @@ static void ti_qspi_setup_clk(struct ti_qspi *qspi, u32 speed_hz)
}
pm_runtime_put_autosuspend(qspi->dev);
+
+ return 0;
}
static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
@@ -621,7 +625,9 @@ static int ti_qspi_exec_mem_op(struct spi_mem *mem,
mutex_lock(&qspi->list_lock);
if (!qspi->mmap_enabled || qspi->current_cs != spi_get_chipselect(mem->spi, 0)) {
- ti_qspi_setup_clk(qspi, op->max_freq);
+ ret = ti_qspi_setup_clk(qspi, op->max_freq);
+ if (ret)
+ goto unlock;
ti_qspi_enable_memory_map(mem->spi);
}
ti_qspi_setup_mmap_read(mem->spi, op->cmd.opcode, op->data.buswidth,
@@ -646,6 +652,7 @@ static int ti_qspi_exec_mem_op(struct spi_mem *mem,
op->data.nbytes);
}
+unlock:
mutex_unlock(&qspi->list_lock);
return ret;
@@ -704,7 +711,11 @@ static int ti_qspi_start_transfer_one(struct spi_controller *host,
wlen = t->bits_per_word >> 3;
transfer_len_words = min(t->len / wlen, frame_len_words);
- ti_qspi_setup_clk(qspi, t->speed_hz);
+ ret = ti_qspi_setup_clk(qspi, t->speed_hz);
+ if (ret) {
+ mutex_unlock(&qspi->list_lock);
+ return ret;
+ }
ret = qspi_transfer_msg(qspi, t, transfer_len_words * wlen);
if (ret) {
dev_dbg(qspi->dev, "transfer message failed\n");
--
2.34.1
next prev parent reply other threads:[~2026-10-19 8:44 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-19 8:44 [PATCH 0/2] spi: handle runtime resume failures Jiale Yao
2026-10-19 8:44 ` [PATCH 1/2] spi: stm32-ospi: handle runtime resume failure in remove Jiale Yao
2026-10-30 14:47 ` Patrice CHOTARD
2026-10-19 8:44 ` Jiale Yao [this message]
2026-10-19 23:57 ` [PATCH 2/2] spi: ti-qspi: handle setup clock runtime resume failure Atsushi Nemoto
2026-11-02 22:39 ` [PATCH 0/2] spi: handle runtime resume failures Mark Brown
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