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Mon, 19 Oct 2026 11:47:50 -0500 From: David Zhang To: , , , , , , CC: David Zhang , , Subject: [PATCH V5 10/19] accel/amdxdna: Refactor AIE4 hardware initialization sequence Date: Mon, 19 Oct 2026 09:47:37 -0700 Message-ID: <20261019164746.827277-11-yidong.zhang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261019164746.827277-1-yidong.zhang@amd.com> References: <20261019164746.827277-1-yidong.zhang@amd.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH1PEPF00062F27:EE_|CH3PR12MB8510:EE_ X-MS-Office365-Filtering-Correlation-Id: 4e2008e4-225f-47b8-ac87-08df2e00c398 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|23010399003|82310400026|1800799024|261009223027099003|10067099003|56012099006|3023799007|6133799003|22082099003|18002099003|11063799006|4143699003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Z6unDV5B9ThAn4JQz+kpPaeDdIGxIh+6FqKijvVhX87FzseVO88szZYRZcrZLGAF0s//TOC1k0X74Dxy4YwSUoUV2oKghSyRG8b1QVfuscNFAHdS8dACMPQQ8r/UtBxgyCbWykSrh8G+j5FKt+6+LOruzKe/npV5kR7NkkCeZcrm9+6Ar3pwt7pEpuIuRhg1Ig3KzA4mDqCWP1TQZ9N5aYA4SVAMyl54cpm26XLTYMZ5/SFXy/fZr67cvWiPKbJfJyzslcOkQbhvLVtgvUQOSbia54YNTEnHvItF5Kx6oR3HLEJAXMWyz3GI5Xe0YTHPdEEBfCHcuWsiJI7peoxwfzrDBbJ1hhDkWvAkq4aTl2M6opPxSXAVdvSI7X1EstQ366ruleewTgGYkKvJ1xNPqBGkhFdxAv0KvfDV+n7MUcXaNRkxz0nJD5uznTLL4Jj9 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2026 16:48:12.5212 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4e2008e4-225f-47b8-ac87-08df2e00c398 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: PH1PEPF00062F27.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8510 Reorganize AIE4 hardware initialization into distinct phases, next to the existing aie4_config_fw(): - aie4_query_fw(): Query NPU and CERT firmware versions. - aie4_setup_aie(): Query AIE version, metadata, initialize DPM frequency table, and initialize partitions. Update aie4_pf_hw_start(), aie4_vf_hw_start(), and aie4_classic_hw_start() to use these phases and unify error unwinding labels. As part of this, aie4_pf_hw_start() now also calls aie4_query_fw(), which it previously did not do. Signed-off-by: David Zhang Reviewed-by: Lizhi Hou --- drivers/accel/amdxdna/aie4_pci.c | 79 +++++++++++++++++++------------- 1 file changed, 46 insertions(+), 33 deletions(-) diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c index f59394d62d9c..544a7d6a02eb 100644 --- a/drivers/accel/amdxdna/aie4_pci.c +++ b/drivers/accel/amdxdna/aie4_pci.c @@ -49,7 +49,7 @@ static int aie4_fw_is_alive(struct amdxdna_dev *xdna) { const struct amdxdna_dev_priv *npriv = xdna->dev_info->dev_priv; struct amdxdna_dev_hdl *ndev = xdna->dev_handle; - u32 __iomem *src; + void __iomem *src; u32 fw_is_valid; int ret; @@ -279,7 +279,8 @@ static void aie4_partition_fini(struct amdxdna_dev_hdl *ndev) XDNA_ERR(xdna, "partition fini failed: %d", ret); } -static int aie4_query(struct amdxdna_dev_hdl *ndev) +/* Verify CERT protocol compatibility before starting hardware. */ +static int aie4_query_fw(struct amdxdna_dev_hdl *ndev) { struct amdxdna_dev *xdna = ndev->aie.xdna; int ret; @@ -292,25 +293,6 @@ static int aie4_query(struct amdxdna_dev_hdl *ndev) if (ret) return ret; - ret = aie4_query_aie_version(ndev, &ndev->aie.version); - if (ret) - return ret; - - ret = aie4_query_aie_metadata(ndev, &ndev->aie.metadata); - if (ret) - return ret; - - ndev->total_col = min_t(u32, AIE4_TOTAL_COLUMN, ndev->aie.metadata.cols); - - ret = aie4_init_dpm_freq_table(ndev); - if (ret) { - if (ret == -ETIME) - return ret; - /* if query dpm from fw failed, using default value */ - if (ndev->priv->hw_ops && ndev->priv->hw_ops->set_dpm) - (void)ndev->priv->hw_ops->set_dpm(&ndev->aie, 0); - } - return 0; } @@ -339,6 +321,32 @@ static int aie4_config_fw(struct amdxdna_dev_hdl *ndev) return 0; } +static int aie4_setup_aie(struct amdxdna_dev_hdl *ndev) +{ + int ret; + + ret = aie4_query_aie_version(ndev, &ndev->aie.version); + if (ret) + return ret; + + ret = aie4_query_aie_metadata(ndev, &ndev->aie.metadata); + if (ret) + return ret; + + ndev->total_col = min_t(u32, AIE4_TOTAL_COLUMN, ndev->aie.metadata.cols); + + ret = aie4_init_dpm_freq_table(ndev); + if (ret) { + if (ret == -ETIME) + return ret; + /* if query dpm from fw failed, using default value */ + if (ndev->priv->hw_ops && ndev->priv->hw_ops->set_dpm) + (void)ndev->priv->hw_ops->set_dpm(&ndev->aie, 0); + } + + return aie4_partition_init(ndev); +} + static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev) { int ret; @@ -351,6 +359,10 @@ static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev) if (ret) goto stop_fw; + ret = aie4_query_fw(ndev); + if (ret) + goto mbox_fini; + ret = aie4_config_fw(ndev); if (ret) goto mbox_fini; @@ -388,13 +400,13 @@ static int aie4_vf_hw_start(struct amdxdna_dev_hdl *ndev) if (ret) return ret; - ret = aie4_query(ndev); + ret = aie4_query_fw(ndev); if (ret) - goto mailbox_fini; + goto mbox_fini; - ret = aie4_partition_init(ndev); + ret = aie4_setup_aie(ndev); if (ret) - goto mailbox_fini; + goto mbox_fini; ret = aie4_restore_power_mode(ndev); if (ret) @@ -404,7 +416,7 @@ static int aie4_vf_hw_start(struct amdxdna_dev_hdl *ndev) partition_fini: aie4_partition_fini(ndev); -mailbox_fini: +mbox_fini: aie4_mailbox_fini(ndev); return ret; } @@ -431,17 +443,17 @@ static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev) if (ret) goto stop_fw; - ret = aie4_query(ndev); + ret = aie4_query_fw(ndev); if (ret) - goto mailbox_fini; + goto mbox_fini; ret = aie4_config_fw(ndev); if (ret) - goto mailbox_fini; + goto mbox_fini; - ret = aie4_partition_init(ndev); + ret = aie4_setup_aie(ndev); if (ret) - goto mailbox_fini; + goto mbox_fini; ret = aie4_restore_power_mode(ndev); if (ret) @@ -451,10 +463,11 @@ static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev) partition_fini: aie4_partition_fini(ndev); -mailbox_fini: +mbox_fini: aie4_mailbox_fini(ndev); stop_fw: aie4_fw_stop(ndev); + return ret; } @@ -528,8 +541,8 @@ static int aie4_prepare_firmware(struct amdxdna_dev_hdl *ndev, void __iomem *tbl[PCI_NUM_RESOURCES]) { struct amdxdna_dev *xdna = ndev->aie.xdna; + struct smu_config smu_conf = {}; struct psp_config psp_conf; - struct smu_config smu_conf; int i; psp_conf.fw_size = npufw->size; -- 2.34.1