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Mon, 19 Oct 2026 11:47:45 -0500 From: David Zhang To: , , , , , , CC: David Zhang , , Subject: [PATCH V5 05/19] accel/amdxdna: Add NPU3 classic device support Date: Mon, 19 Oct 2026 09:47:32 -0700 Message-ID: <20261019164746.827277-6-yidong.zhang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261019164746.827277-1-yidong.zhang@amd.com> References: <20261019164746.827277-1-yidong.zhang@amd.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH1PEPF00062F2A:EE_|CH1PPF2EB7CF87B:EE_ X-MS-Office365-Filtering-Correlation-Id: 34e1a07c-dffd-452e-7af0-08df2e00b9f0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|82310400026|1800799024|376014|18002099003|22082099003|3023799007|11063799006|4143699003|10067099003|261009223027099003|56012099006; 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Remove device IDs 0x1B0B and 0x1B0C because those devices will not be released. Suspend and resume support is added in a later patch, once the kernel-mode queue (KMQ) can drain in-flight commands. Signed-off-by: David Zhang Reviewed-by: Lizhi Hou --- drivers/accel/amdxdna/aie4_pci.c | 83 +++++++++++++++++++++++++ drivers/accel/amdxdna/aie4_pci.h | 1 + drivers/accel/amdxdna/amdxdna_pci_drv.c | 23 ++++--- drivers/accel/amdxdna/amdxdna_pci_drv.h | 1 + drivers/accel/amdxdna/npu3_regs.c | 14 +++++ 5 files changed, 115 insertions(+), 7 deletions(-) diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c index e9cd2af224d3..1eeb1cb73b27 100644 --- a/drivers/accel/amdxdna/aie4_pci.c +++ b/drivers/accel/amdxdna/aie4_pci.c @@ -366,6 +366,51 @@ static void aie4_vf_hw_stop(struct amdxdna_dev_hdl *ndev) aie4_mailbox_fini(ndev); } +static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev) +{ + int ret; + + ret = aie4_fw_start(ndev); + if (ret) + return ret; + + ret = aie4_mailbox_init(ndev); + if (ret) + goto stop_fw; + + ret = aie4_query(ndev); + if (ret) + goto mailbox_fini; + + ret = aie4_attach_work_buffer(ndev); + if (ret) + goto mailbox_fini; + + ret = aie4_partition_init(ndev); + if (ret) + goto mailbox_fini; + + return 0; + +mailbox_fini: + aie4_mailbox_fini(ndev); +stop_fw: + aie4_fw_stop(ndev); + return ret; +} + +static void aie4_classic_hw_stop(struct amdxdna_dev_hdl *ndev) +{ + struct amdxdna_dev *xdna = ndev->aie.xdna; + + drm_WARN_ON(&xdna->ddev, !mutex_is_locked(&xdna->dev_lock)); + + aie4_partition_fini(ndev); + aie4_suspend_fw(ndev); + aie4_mailbox_fini(ndev); + aie4_fw_stop(ndev); +} + static int aie4_request_firmware(struct amdxdna_dev_hdl *ndev, const struct firmware **npufw, const struct firmware **certfw) @@ -628,6 +673,29 @@ static int aie4_vf_init(struct amdxdna_dev *xdna) return aie4_vf_hw_start(xdna->dev_handle); } +static int aie4_classic_init(struct amdxdna_dev *xdna) +{ + int ret; + + ret = aie4m_pcidev_init(xdna); + if (ret) + return ret; + + ret = aie4_alloc_work_buffer(xdna->dev_handle); + if (ret) + return ret; + + ret = aie4_classic_hw_start(xdna->dev_handle); + if (ret) + goto free_work_buf; + + return 0; + +free_work_buf: + aie4_free_work_buffer(xdna->dev_handle); + return ret; +} + static void aie4_pf_fini(struct amdxdna_dev *xdna) { aie4_sriov_stop(xdna->dev_handle); @@ -640,6 +708,12 @@ static void aie4_vf_fini(struct amdxdna_dev *xdna) aie4_vf_hw_stop(xdna->dev_handle); } +static void aie4_classic_fini(struct amdxdna_dev *xdna) +{ + aie4_classic_hw_stop(xdna->dev_handle); + aie4_free_work_buffer(xdna->dev_handle); +} + const struct amdxdna_dev_ops aie4_pf_ops = { .init = aie4_pf_init, .fini = aie4_pf_fini, @@ -654,3 +728,12 @@ const struct amdxdna_dev_ops aie4_vf_ops = { .cmd_wait = aie4_cmd_wait, .get_aie_info = aie4_get_info, }; + +const struct amdxdna_dev_ops aie4_classic_ops = { + .init = aie4_classic_init, + .fini = aie4_classic_fini, + .hwctx_init = aie4_hwctx_init, + .hwctx_fini = aie4_hwctx_fini, + .cmd_wait = aie4_cmd_wait, + .get_aie_info = aie4_get_info, +}; diff --git a/drivers/accel/amdxdna/aie4_pci.h b/drivers/accel/amdxdna/aie4_pci.h index bdbb2d7cf0e7..940e67347d74 100644 --- a/drivers/accel/amdxdna/aie4_pci.h +++ b/drivers/accel/amdxdna/aie4_pci.h @@ -96,5 +96,6 @@ static inline int aie4_sriov_stop(struct amdxdna_dev_hdl *ndev) extern const struct amdxdna_dev_ops aie4_pf_ops; extern const struct amdxdna_dev_ops aie4_vf_ops; +extern const struct amdxdna_dev_ops aie4_classic_ops; #endif /* _AIE4_PCI_H_ */ diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.c b/drivers/accel/amdxdna/amdxdna_pci_drv.c index 0842fd31c9f2..a8c29546d49c 100644 --- a/drivers/accel/amdxdna/amdxdna_pci_drv.c +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.c @@ -29,8 +29,14 @@ MODULE_FIRMWARE("amdnpu/17f0_20/npu.sbin"); MODULE_FIRMWARE("amdnpu/1502_00/npu_7.sbin"); MODULE_FIRMWARE("amdnpu/17f0_10/npu_7.sbin"); MODULE_FIRMWARE("amdnpu/17f0_11/npu_7.sbin"); +MODULE_FIRMWARE("amdnpu/17f1_10/npu.sbin"); +MODULE_FIRMWARE("amdnpu/17f1_10/cert.sbin"); MODULE_FIRMWARE("amdnpu/17f2_10/npu.sbin"); MODULE_FIRMWARE("amdnpu/17f2_10/cert.sbin"); +MODULE_FIRMWARE("amdnpu/17f1_13/npu.sbin"); +MODULE_FIRMWARE("amdnpu/17f1_13/cert.sbin"); +MODULE_FIRMWARE("amdnpu/17f2_13/npu.sbin"); +MODULE_FIRMWARE("amdnpu/17f2_13/cert.sbin"); /* * 0.0: Initial version @@ -56,10 +62,9 @@ MODULE_FIRMWARE("amdnpu/17f2_10/cert.sbin"); static const struct pci_device_id pci_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1502) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f0) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f1) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f2) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x17f3) }, - { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1B0B) }, - { PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x1B0C) }, {0} }; @@ -70,10 +75,12 @@ static const struct amdxdna_device_id amdxdna_ids[] = { { 0x17f0, 0x10, &dev_npu4_info }, { 0x17f0, 0x11, &dev_npu5_info }, { 0x17f0, 0x20, &dev_npu6_info }, + { 0x17f1, 0x10, &dev_npu3_classic_info }, { 0x17f2, 0x10, &dev_npu3_pf_info }, { 0x17f3, 0x10, &dev_npu3_vf_info }, - { 0x1B0B, 0x10, &dev_npu3_pf_info }, - { 0x1B0C, 0x10, &dev_npu3_vf_info }, + { 0x17f1, 0x13, &dev_npu3_classic_info }, + { 0x17f2, 0x13, &dev_npu3_pf_info }, + { 0x17f3, 0x13, &dev_npu3_vf_info }, {0} }; @@ -141,8 +148,9 @@ static int amdxdna_drm_open(struct drm_device *ddev, struct drm_file *filp) mmgrab(client->mm); xa_init_flags(&client->hwctx_xa, XA_FLAGS_ALLOC); xa_init_flags(&client->dev_heap_xa, XA_FLAGS_ALLOC); - drm_mm_init(&client->dev_heap_mm, xdna->dev_info->dev_mem_base, - xdna->dev_info->dev_heap_max_size); + if (xdna->dev_info->dev_heap_max_size) + drm_mm_init(&client->dev_heap_mm, xdna->dev_info->dev_mem_base, + xdna->dev_info->dev_heap_max_size); mutex_init(&client->mm_lock); mutex_lock(&xdna->client_lock); @@ -179,7 +187,8 @@ static void amdxdna_client_cleanup(struct amdxdna_client *client) xa_for_each(&client->dev_heap_xa, heap_id, heap) drm_gem_object_put(to_gobj(heap)); xa_destroy(&client->dev_heap_xa); - drm_mm_takedown(&client->dev_heap_mm); + if (client->xdna->dev_info->dev_heap_max_size) + drm_mm_takedown(&client->dev_heap_mm); mutex_destroy(&client->mm_lock); mmdrop(client->mm); diff --git a/drivers/accel/amdxdna/amdxdna_pci_drv.h b/drivers/accel/amdxdna/amdxdna_pci_drv.h index 1b044646cc8a..11f4cc53d45f 100644 --- a/drivers/accel/amdxdna/amdxdna_pci_drv.h +++ b/drivers/accel/amdxdna/amdxdna_pci_drv.h @@ -178,6 +178,7 @@ struct amdxdna_client { /* Add device info below */ extern const struct amdxdna_dev_info dev_npu1_info; +extern const struct amdxdna_dev_info dev_npu3_classic_info; extern const struct amdxdna_dev_info dev_npu3_pf_info; extern const struct amdxdna_dev_info dev_npu3_vf_info; extern const struct amdxdna_dev_info dev_npu4_info; diff --git a/drivers/accel/amdxdna/npu3_regs.c b/drivers/accel/amdxdna/npu3_regs.c index 93f749acb5d5..c82433d62901 100644 --- a/drivers/accel/amdxdna/npu3_regs.c +++ b/drivers/accel/amdxdna/npu3_regs.c @@ -105,3 +105,17 @@ const struct amdxdna_dev_info dev_npu3_vf_info = { .cert_feature_tbl = npu3_cert_feature_table, .ops = &aie4_vf_ops, }; + +const struct amdxdna_dev_info dev_npu3_classic_info = { + .mbox_bar = NPU3_MBOX_BAR, + .sram_bar = NPU3_MBOX_BUFFER_BAR, + .psp_bar = NPU3_PSP_BAR_INDEX, + .smu_bar = NPU3_SMU_BAR_INDEX, + .doorbell_bar = NPU3_DOORBELL_BAR, + .default_vbnv = "RyzenAI-npu3", + .device_type = AMDXDNA_DEV_TYPE_UMQ, + .dev_priv = &npu3_dev_priv, + .fw_feature_tbl = npu3_fw_feature_table, + .cert_feature_tbl = npu3_cert_feature_table, + .ops = &aie4_classic_ops, +}; -- 2.34.1