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Tue, 20 Oct 2026 07:54:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1792482881; bh=3GqzT7SXZUXUviYJRJR+eWJ2kJqwUKNfSUL8dK6KjqY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To; b=TRvi82LizuZMWTakwcrNYrnbsYG2NEBKalyLRcdcAi8HbpbefAbzdGtI3uRfigqlz vfe0/tZJeypxMX5oXbLW76DMqU9u047doKdzEiMxinQTb4clbyBeI8X8F5+QAPSkx5 PzXBeE1aJ4IaoV9HhceehvuUx81BlTBdG7zcHjTsDSBI6YvWIl/LaTyaE5Sib0tnVp +KckY5jBI1/THkIm/TznNxt4FL+6617pZ7ZcYKj864+zh5+5Ht/g9fLcIJN+ozuXCc lsMAufq8XCXdHqpJZyLmrpQtAzzC2gqeb32nM48+aP5QE7F3GK26Ue3ELgLqms+809 zMSj2scCa6gGg== Received: from nexus.subspace.kernel.org (localhost [IPv6:::1]) by lkml.kernel.org (Postfix) with ESMTP id 76FCF4307D; Tue, 20 Oct 2026 07:54:40 +0000 (UTC) From: Long Zhao via B4 Relay Date: Tue, 20 Oct 2026 15:54:05 +0800 Subject: [PATCH v11 1/9] dt-bindings: gpio: pl061: add Ambarella CV75 variant X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Message-Id: <20261020-cv75-gpio-v11-1-e058bae19571@ambarella.com> References: <20261020-cv75-gpio-v11-0-e058bae19571@ambarella.com> In-Reply-To: <20261020-cv75-gpio-v11-0-e058bae19571@ambarella.com> To: Bartosz Golaszewski , linux-gpio@vger.kernel.org Cc: Linus Walleij , Michael Walle , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Krzysztof Kozlowski , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, Long Zhao , Long Zhao , linux-kernel@vger.kernel.org, Conor Dooley X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792482877; l=2175; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=ecrzSAMMaNZiFiJHNHyvnNwBNYVIUrMbREC+e46Wpqs=; b=YOYD8ndIEW5jjxPRKsjVacPtkyWhlYjHe4G0+bpfwyS7N7QGIaLdKr7PjB8EUbPIjQGA5Vdk2 mEoPMlH4LPABS53ye4h/nsnXPNhcz8mv+DLap6gisDzmLUk6l4PVzdf X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com Content-Transfer-Encoding: 7bit From: Long Zhao The CV75 GPIO is a modified PL061. The basic registers have the same names and roles (DAT/DIR/IS/IBE/IEV/IE/MIS/IC). Each bank is 32-bit and 32 lines and adds MASK and ENABLE, so it is not register-compatible with the ARM PL061 and arm,pl061 must not be used as a fallback. The AMBA core matches the PL061 driver by PrimeCell ID, not by the DT compatible string. These blocks do not implement the standard PL061 ID (0x00041061) in the ID registers, so arm,primecell-periphid is required and is fixed to 0x000e8061; the driver uses that ID to select the Ambarella layout. gpio-ranges is required because each bank is a slice of the SoC pinctrl pin space. Acked-by: Conor Dooley Reviewed-by: Linus Walleij Signed-off-by: Long Zhao --- .../devicetree/bindings/gpio/pl061-gpio.yaml | 25 +++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml b/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml index 4d970e55104b..c22dd8a1d2c1 100644 --- a/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/pl061-gpio.yaml @@ -15,7 +15,9 @@ select: properties: compatible: contains: - const: arm,pl061 + enum: + - arm,pl061 + - ambarella,cv75-gpio required: - compatible @@ -25,7 +27,9 @@ properties: compatible: items: - - const: arm,pl061 + - enum: + - ambarella,cv75-gpio + - arm,pl061 - const: arm,primecell reg: @@ -64,6 +68,21 @@ required: - "#gpio-cells" - gpio-controller -additionalProperties: false +allOf: + - $ref: /schemas/arm/primecell.yaml# + - if: + properties: + compatible: + contains: + const: ambarella,cv75-gpio + then: + properties: + arm,primecell-periphid: + const: 0x000e8061 + required: + - arm,primecell-periphid + - gpio-ranges + +unevaluatedProperties: false ... -- 2.34.1