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([39.170.101.209]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ad64273f6csm1479185a91.15.2026.10.19.19.57.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2026 19:57:08 -0700 (PDT) From: Ping Li To: ben.horgan@arm.com, james.morse@arm.com Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, reinette.chatre@intel.com, fenghuay@nvidia.com Subject: Re: [PATCH] arm_mpam: Do not access MPAMF_ESR on MSCs that do not have it Date: Tue, 20 Oct 2026 10:57:04 +0800 Message-Id: <20261020025704.1516317-1-leeonion.muyu@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <4bf21ff8-7e4b-4afe-b3e9-9ee85fcd1c84@arm.com> References: <4bf21ff8-7e4b-4afe-b3e9-9ee85fcd1c84@arm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Ben, You are right, thanks for the pointers to the spec. Our MSC is an MPAM v1.0 implementation without MPAMF_ESR, and the RTL responds to accesses of unimplemented registers with a bus error instead of RAZ/WI - which is what motivated the patch. Reading MPAMF_ESR from the CPU therefore raises an external abort rather than reading as zero. Per RLNXX this implementation is not compliant, so the fix belongs in hardware: the MSC design team will change accesses to unimplemented registers to be RAZ/WI, as the specification requires. With that in place the existing driver code is safe, so I am withdrawing this patch. Thanks, Ping