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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=valinux.co.jp; Received: from TY7P286MB6866.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:325::11) by OS9P286MB7503.JPNP286.PROD.OUTLOOK.COM (2603:1096:604:44f::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.522.19; Tue, 20 Oct 2026 03:11:00 +0000 Received: from TY7P286MB6866.JPNP286.PROD.OUTLOOK.COM ([fe80::cce5:2aa8:53f9:dba9]) by TY7P286MB6866.JPNP286.PROD.OUTLOOK.COM ([fe80::cce5:2aa8:53f9:dba9%5]) with mapi id 15.21.0522.017; Tue, 20 Oct 2026 03:10:59 +0000 From: Koichiro Den To: Marek Vasut , Geert Uytterhoeven , Yoshihiro Shimoda , Shawn Lin , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Magnus Damm , Jingoo Han Cc: Philipp Zabel , Frank Li , Niklas Cassel , Wilfred Mallawa , Serge Semin , linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 02/17] PCI: dwc: Factor out the PORT_LINK_DEBUG1 link-up check Date: Tue, 20 Oct 2026 12:10:34 +0900 Message-ID: <20261020031049.969895-3-den@valinux.co.jp> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20261020031049.969895-1-den@valinux.co.jp> References: <20261020031049.969895-1-den@valinux.co.jp> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: TYCP286CA0036.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:29d::20) To TY7P286MB6866.JPNP286.PROD.OUTLOOK.COM (2603:1096:405:325::11) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY7P286MB6866:EE_|OS9P286MB7503:EE_ X-MS-Office365-Filtering-Correlation-Id: 59ba7abd-d144-4e69-8926-08df2e57c433 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|366016|7416014|1800799024|376014|10070799003|22082099003|18002099003|921020|10067099003|261009223027099003|56012099006; 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A callback that needs a platform-specific check on top of that register would have to duplicate the register read. Factor the check out into dw_pcie_link_up_debug_check() and export it for modular glue drivers. pcie-rcar-gen4 will be the first user: its APP link-up events remain latched after the link goes down, so it has to combine them with the live PORT_LINK_DEBUG1 state. No functional change. Suggested-by: Marek Vasut Reviewed-by: Shawn Lin Reviewed-by: Marek Vasut Signed-off-by: Koichiro Den --- Changes since v4: - Add Reviewed-by tags from Shawn and Marek. No code changes. drivers/pci/controller/dwc/pcie-designware.c | 15 +++++++++++---- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index c726aa71c830..49a9ba910ba8 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -817,17 +817,24 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci) } EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link); -bool dw_pcie_link_up(struct dw_pcie *pci) +/* Link state from PORT_LINK_DEBUG1: up and not in training */ +bool dw_pcie_link_up_debug_check(struct dw_pcie *pci) { u32 val; - if (pci->ops && pci->ops->link_up) - return pci->ops->link_up(pci); - val = dw_pcie_readl_dbi(pci, PORT_LINK_DEBUG1); return ((val & PORT_LINK_DEBUG1_LINK_UP) && (!(val & PORT_LINK_DEBUG1_LINK_IN_TRAINING))); } +EXPORT_SYMBOL_GPL(dw_pcie_link_up_debug_check); + +bool dw_pcie_link_up(struct dw_pcie *pci) +{ + if (pci->ops && pci->ops->link_up) + return pci->ops->link_up(pci); + + return dw_pcie_link_up_debug_check(pci); +} EXPORT_SYMBOL_GPL(dw_pcie_link_up); void dw_pcie_upconfig_setup(struct dw_pcie *pci) diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 419932488280..2ce61709b58c 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -618,6 +618,7 @@ int dw_pcie_write(void __iomem *addr, int size, u32 val); u32 dw_pcie_read_dbi(struct dw_pcie *pci, u32 reg, size_t size); void dw_pcie_write_dbi(struct dw_pcie *pci, u32 reg, size_t size, u32 val); void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, size_t size, u32 val); +bool dw_pcie_link_up_debug_check(struct dw_pcie *pci); bool dw_pcie_link_up(struct dw_pcie *pci); void dw_pcie_upconfig_setup(struct dw_pcie *pci); int dw_pcie_wait_for_link(struct dw_pcie *pci); -- 2.54.0