From: Koichiro Den <den@valinux.co.jp>
To: "Marek Vasut" <marek.vasut+renesas@mailbox.org>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Yoshihiro Shimoda" <yoshihiro.shimoda.uh@renesas.com>,
"Shawn Lin" <Shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Magnus Damm" <magnus.damm@gmail.com>,
"Jingoo Han" <jingoohan1@gmail.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
Frank Li <Frank.Li@nxp.com>, Niklas Cassel <cassel@kernel.org>,
Wilfred Mallawa <wilfred.mallawa@wdc.com>,
Serge Semin <fancer.lancer@gmail.com>,
linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v5 08/17] PCI: rcar-gen4: Separate hardware setup from resource acquisition
Date: Tue, 20 Oct 2026 12:10:40 +0900 [thread overview]
Message-ID: <20261020031049.969895-9-den@valinux.co.jp> (raw)
In-Reply-To: <20261020031049.969895-1-den@valinux.co.jp>
Factor out the hardware setup needed by Root Port recovery into helpers.
Recovery needs to reset and restore the controller while keeping its
clocks enabled and the R-Car Gen5 SoC PHY initialized.
- From rcar_gen4_pcie_common_init(), extract the power reset and mode
setup. Leave clock enabling and Application/Local reset control in
common_init(), so recovery can keep the APP registers accessible.
- From rcar_gen4_v4h_v4m_pcie_init() and rcar_gen5_pcie_init(), extract
the SoC-specific register setup. This allows recovery to restore those
settings without taking another clock or PHY initialization reference.
- From rcar_gen4_pcie_host_init(), extract the Root Port register setup
and PERST# release. Both paths need this host-specific sequence after
the per-SoC initialization or reset.
No functional changes.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Koichiro Den <den@valinux.co.jp>
---
Changes since v3:
- No changes.
drivers/pci/controller/dwc/pcie-rcar-gen4.c | 125 ++++++++++++--------
1 file changed, 77 insertions(+), 48 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index e1b748a9d58b..cbd22e6bb44b 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -234,20 +234,13 @@ static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
rcar->drvdata->ltssm_control(rcar, false);
}
-static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
+/* Clocks must be enabled and the Application/Local reset deasserted. */
+static int rcar_gen4_pcie_reset(struct rcar_gen4_pcie *rcar)
{
struct dw_pcie *dw = &rcar->dw;
u32 val;
int ret;
- ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
- if (ret) {
- dev_err(dw->dev, "Enabling core clocks failed\n");
- return ret;
- }
-
- reset_control_deassert(dw->core_rsts[DW_PCIE_CORE_RST].rstc);
-
if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc)) {
reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
/*
@@ -266,8 +259,7 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
} else if (rcar->drvdata->mode == DW_PCIE_EP_TYPE) {
val |= DEVICE_TYPE_EP;
} else {
- ret = -EINVAL;
- goto err_unprepare;
+ return -EINVAL;
}
if (dw->num_lanes < 4)
@@ -277,7 +269,7 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
ret = reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
if (ret)
- goto err_unprepare;
+ return ret;
/*
* Assure the reset is latched and the core is ready for DBI access.
@@ -293,6 +285,26 @@ static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
fsleep(1000);
return 0;
+}
+
+static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
+{
+ struct dw_pcie *dw = &rcar->dw;
+ int ret;
+
+ ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
+ if (ret) {
+ dev_err(dw->dev, "Enabling core clocks failed\n");
+ return ret;
+ }
+
+ reset_control_deassert(dw->core_rsts[DW_PCIE_CORE_RST].rstc);
+
+ ret = rcar_gen4_pcie_reset(rcar);
+ if (ret)
+ goto err_unprepare;
+
+ return 0;
err_unprepare:
reset_control_assert(dw->core_rsts[DW_PCIE_CORE_RST].rstc);
@@ -310,16 +322,10 @@ static void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar)
clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
}
-static int rcar_gen4_v4h_v4m_pcie_init(struct rcar_gen4_pcie *rcar)
+static void rcar_gen4_v4h_v4m_pcie_configure(struct rcar_gen4_pcie *rcar)
{
struct dw_pcie *dw = &rcar->dw;
u32 val;
- int ret;
-
- /* R-Car Gen4 common initialization. */
- ret = rcar_gen4_pcie_common_init(rcar);
- if (ret)
- return ret;
/* R-Car V4H and V4M specific additional initialization. */
val = dw_pcie_readl_dbi(dw, PORT_LANE_SKEW);
@@ -331,6 +337,17 @@ static int rcar_gen4_v4h_v4m_pcie_init(struct rcar_gen4_pcie *rcar)
val = readl(rcar->base + PCIEPWRMNGCTRL);
val |= APP_CLK_REQ_N | APP_CLK_PM_EN;
writel(val, rcar->base + PCIEPWRMNGCTRL);
+}
+
+static int rcar_gen4_v4h_v4m_pcie_init(struct rcar_gen4_pcie *rcar)
+{
+ int ret;
+
+ ret = rcar_gen4_pcie_common_init(rcar);
+ if (ret)
+ return ret;
+
+ rcar_gen4_v4h_v4m_pcie_configure(rcar);
return 0;
}
@@ -341,22 +358,11 @@ static void rcar_gen5_pcie_deinit(struct rcar_gen4_pcie *rcar)
rcar_gen4_pcie_common_deinit(rcar);
}
-static int rcar_gen5_pcie_init(struct rcar_gen4_pcie *rcar)
+static void rcar_gen5_pcie_configure(struct rcar_gen4_pcie *rcar)
{
struct dw_pcie *dw = &rcar->dw;
- int ret;
u32 val;
- /* R-Car Gen4 and Gen5 common initialization. */
- ret = rcar_gen4_pcie_common_init(rcar);
- if (ret)
- return ret;
-
- /* R-Car Gen5 specific additional initialization. */
- ret = phy_init(rcar->phy);
- if (ret)
- goto err_unprepare;
-
dw_pcie_dbi_ro_wr_en(dw);
val = dw_pcie_readl_dbi(dw, PORT_LANE_SKEW);
@@ -375,13 +381,25 @@ static int rcar_gen5_pcie_init(struct rcar_gen4_pcie *rcar)
val |= APP_CLK_REQ_N | APP_CLK_PM_EN |
APP_READY_ENTR_L23 | APP_REQ_ENTR_L1;
writel(val, rcar->base + PCIEPWRMNGCTRL);
+}
- return 0;
+static int rcar_gen5_pcie_init(struct rcar_gen4_pcie *rcar)
+{
+ int ret;
-err_unprepare:
- rcar_gen4_pcie_common_deinit(rcar);
+ ret = rcar_gen4_pcie_common_init(rcar);
+ if (ret)
+ return ret;
- return ret;
+ ret = phy_init(rcar->phy);
+ if (ret) {
+ rcar_gen4_pcie_common_deinit(rcar);
+ return ret;
+ }
+
+ rcar_gen5_pcie_configure(rcar);
+
+ return 0;
}
static int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
@@ -619,21 +637,11 @@ static void rcar_gen4_pcie_host_perst_assert(struct dw_pcie_rp *pp, bool assert)
}
/* Host mode */
-static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
+static int rcar_gen4_pcie_host_setup(struct dw_pcie_rp *pp)
{
struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
- struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
int ret;
- if (pp->bridge)
- pp->bridge->enable_device = rcar_gen4_pcie_enable_device;
-
- rcar_gen4_pcie_host_perst_assert(pp, true);
-
- ret = rcar->drvdata->init(rcar);
- if (ret)
- return ret;
-
/*
* According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
* Rev.5.20a and 3.5.6.1 "RC mode" in DWC PCIe RC databook v5.20a, we
@@ -645,13 +653,34 @@ static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
ret = rcar_gen4_pcie_host_msi_init(pp);
if (ret)
- goto err;
+ return ret;
msleep(PCIE_T_PVPERL_MS); /* pe_rst requires 100msec delay */
-
rcar_gen4_pcie_host_perst_assert(pp, false);
return 0;
+}
+
+static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
+{
+ struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
+ struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
+ int ret;
+
+ if (pp->bridge)
+ pp->bridge->enable_device = rcar_gen4_pcie_enable_device;
+
+ rcar_gen4_pcie_host_perst_assert(pp, true);
+
+ ret = rcar->drvdata->init(rcar);
+ if (ret)
+ return ret;
+
+ ret = rcar_gen4_pcie_host_setup(pp);
+ if (ret)
+ goto err;
+
+ return 0;
err:
rcar->drvdata->deinit(rcar);
--
2.54.0
next prev parent reply other threads:[~2026-10-20 3:11 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-20 3:10 [PATCH v5 00/17] PCI: rcar-gen4: Recover from link down and route Root Port interrupts Koichiro Den
2026-10-20 3:10 ` [PATCH v5 01/17] PCI: dwc: Add Renesas to the RAS DES VSEC list Koichiro Den
2026-10-20 3:10 ` [PATCH v5 02/17] PCI: dwc: Factor out the PORT_LINK_DEBUG1 link-up check Koichiro Den
2026-10-20 3:10 ` [PATCH v5 03/17] PCI: rcar-gen4: Check live link status in link_up() Koichiro Den
2026-10-20 3:10 ` [PATCH v5 04/17] dt-bindings: PCI: rcar-gen4: Add optional "aer" interrupt for R-Car Gen4 SoCs Koichiro Den
2026-10-20 12:45 ` Marek Vasut
2026-10-20 3:10 ` [PATCH v5 05/17] PCI: dwc: Export dw_handle_msi_irq() Koichiro Den
2026-10-20 3:10 ` [PATCH v5 06/17] PCI: rcar-gen4: Move deinitialization helpers before SoC initialization Koichiro Den
2026-10-20 3:10 ` [PATCH v5 07/17] PCI: rcar-gen4: Assert resets when Gen5 SoC PHY initialization fails Koichiro Den
2026-10-20 3:10 ` Koichiro Den [this message]
2026-10-20 3:10 ` [PATCH v5 09/17] PCI: rcar-gen4: Add Root Port reset support Koichiro Den
2026-10-20 3:10 ` [PATCH v5 10/17] PCI: dwc: Free the MSI domain after the host .deinit() callback Koichiro Den
2026-10-20 3:54 ` Shawn Lin
2026-10-20 6:41 ` Koichiro Den
2026-10-20 7:00 ` Shawn Lin
2026-10-20 7:21 ` Koichiro Den
2026-10-20 11:47 ` Geert Uytterhoeven
2026-10-20 13:45 ` Koichiro Den
2026-10-20 3:10 ` [PATCH v5 11/17] PCI: rcar-gen4: Take over the iMSI-RX interrupt Koichiro Den
2026-10-20 3:10 ` [PATCH v5 12/17] PCI: rcar-gen4: Recover the Root Port on link down Koichiro Den
2026-10-20 3:10 ` [PATCH v5 13/17] PCI: rcar-gen4: Route Root Port AER to a virtual Root Port IRQ Koichiro Den
2026-10-21 0:19 ` Marek Vasut
2026-10-20 3:10 ` [PATCH v5 14/17] PCI: rcar-gen4: Route Root Port PME and bandwidth notifications Koichiro Den
2026-10-20 3:10 ` [PATCH v5 15/17] arm64: dts: renesas: r8a779f0: Describe the PCIe AER interrupts Koichiro Den
2026-10-20 3:10 ` [PATCH v5 16/17] arm64: dts: renesas: r8a779g0: " Koichiro Den
2026-10-20 3:10 ` [PATCH v5 17/17] arm64: dts: renesas: r8a779h0: Describe the PCIe AER interrupt Koichiro Den
2026-10-20 8:03 ` [PATCH v5 00/17] PCI: rcar-gen4: Recover from link down and route Root Port interrupts Geert Uytterhoeven
2026-10-20 8:45 ` Koichiro Den
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