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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1831ca95700sm33197858c88.23.2026.10.19.23.18.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 19 Oct 2026 23:18:17 -0700 (PDT) From: Peter Chen To: Vinod Koul Cc: Neil Armstrong , Manivannan Sadhasivam , Konrad Dybcio , Elson Serrao , Ronak Raheja , Wesley Cheng , Udipto Goswami , Jack Pham , Pratham Pratap , Krishna Kurapati , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Chen Subject: [PATCH 1/1] phy: qualcomm: m31-eusb2: Add register XCFGI_159_152 for SE0 recovery Date: Mon, 19 Oct 2026 23:18:11 -0700 Message-ID: <20261020061811.3127511-1-peter.chen@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIwMDAyNCBTYWx0ZWRfX6XR+hmM8zd16 NfGr9RZE53GwgEjkCG8HIw5CXh7Ewhnb6opmNBEwTk6s/siiRAjsFdbpZO1fyeHCMdrV9XtccNb wUqPlW4Ke6xicZk20mLoz+OLbl6lKOc= X-Proofpoint-GUID: DVUjv8JHvJZXyP-v3EM-R2l6OqEI8akI X-Proofpoint-ORIG-GUID: DVUjv8JHvJZXyP-v3EM-R2l6OqEI8akI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIwMDAyNCBTYWx0ZWRfX46MwsRwyirqO uB6HXS5I5JTpPLep3t0Qqcyg7uImMEDyXdrqXdShIzqLqPTFEzVhKNckAqNrJgM5bxIKZBzw5wD rV4a8uZn33u/tUr8F5DyX1yUdA/JWyGaoAwLGw3xPosvnEf1t60txnsevzIkv3sXpEdLGm0xdoM aIQER4ayb1dP+GVRPrDKxZcC9Vna+lRpZa6MHhVBIG8SCLLJGC+LC3+h08gTV0bD5Wxpyoetpfq 1E5vPPgi9ThcgAaESjTHCSaWdc8GwqzUIHBwQ18cTyBO/qDwhpi0xCwd+mcaouTCTq0tiSr569h 6hQMFBIlXmdUWofMaI8DvEPrzEx1Pc2CmU1cBYABZeuO8Jrm1RJ8bG4UUumrPTqkdNiZsMxHNjE KXV4MJvP9olT1fjYhIbQQvk2eJEZv3f3zs5y8OgypmZT57m51tixazpXmIPgpLgaaDi+J7xIde3 Y12w9nemOy/JiY3YsKg== X-Authority-Analysis: v=2.4 cv=TcsDJhQh c=1 sm=1 tr=0 ts=6ad707ab cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=fkmqLtjFOitS6APqvyEA:9 a=Fk4IpSoW4aLDllm1B1p-:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-20_01,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 impostorscore=0 suspectscore=0 spamscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610200024 From: Elson Serrao This patch introduces support for the XCFGI_159_152 register to enable a hardware-based SE0 recovery mechanism in the M31 PHY when operating in host mode. During PHY initialization, spurious pulses from external devices can interfere with speed negotiation, potentially leading to abnormal behavior. To mitigate this, the M31 PHY provides a fail-safe mechanism controlled by bit 159 of the XCFGI register. When XCFG_SE0_TIMEOUT_EN (bit 159) is set, a hardware counter is activated to monitor the SE0 state. If SE0 persists for more than 2.5 ms before entering L0 mode, the PHY interprets this as bus inactivity and resets the state machine to its default state. After transitioning to L0, the PHY resumes normal operation in accordance with the eUSB specification. Signed-off-by: Elson Serrao Signed-off-by: Peter Chen --- drivers/phy/qualcomm/phy-qcom-m31-eusb2.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c index 275df38256de..8d954e772585 100644 --- a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c @@ -56,6 +56,9 @@ #define USB_PHY_XCFGI_7_0 (0x15c) #define PLL_LOCK_TIME GENMASK(1, 0) +#define USB_PHY_XCFGI_159_152 (0x1a8) +#define SE0_TIMEOUT_EN BIT(7) + #define M31_EUSB_PHY_INIT_CFG(o, b, v) \ { \ .off = o, \ @@ -88,6 +91,13 @@ static const struct m31_phy_tbl_entry m31_eusb2_setup_tbl[] = { }; static const struct m31_phy_tbl_entry m31_eusb_phy_override_tbl[] = { + /* + * Set XCFGI[159] to enable SE0 timeout mechanism in M31. + * This enables a counter which will assume bus inactive if + * SE0 is more than 2.5ms and reset the state machine to default + * state. + */ + M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_159_152, SE0_TIMEOUT_EN, 1), M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_39_32, HSTX_PE, 0), M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_71_64, HSTX_SWING, 7), M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_31_24, HSTX_SLEW, 0), -- 2.43.0