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Tue, 20 Oct 2026 06:49:58 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.89]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4j831x01gPz3hhTD; Tue, 20 Oct 2026 06:49:57 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20261020063835epcas5p2d869b6a168944982aebd5defa736bba0~gKYgGN7AV2333523335epcas5p23; Tue, 20 Oct 2026 06:38:35 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20261020063833epsmtip108705944dd0b2e4142e079a6a0b4d202~gKYdvlOyP0323303233epsmtip1G; Tue, 20 Oct 2026 06:38:33 +0000 (GMT) From: Raghav Sharma To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, peter.griffin@linaro.org, alim.akhtar@samsung.com, sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, conor+dt@kernel.org, raghav.s@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, is.gandhi@samsung.com, ts.amit@samsung.com, pokala.reddy@samsung.com Subject: [PATCH v3 13/14] arm64: dts: exynos8855: add cmu_hsi clock DT nodes Date: Tue, 20 Oct 2026 12:25:57 +0530 Message-Id: <20261020065558.1829402-14-raghav.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261020065558.1829402-1-raghav.s@samsung.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CMS-MailID: 20261020063835epcas5p2d869b6a168944982aebd5defa736bba0 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-543,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20261020063835epcas5p2d869b6a168944982aebd5defa736bba0 References: <20261020065558.1829402-1-raghav.s@samsung.com> Add required dt node for cmu_hsi block, while at it add sysreg_hsi node which contians bits for DRCG and MEMCLK which are used by clock driver Signed-off-by: Alim Akhtar Signed-off-by: Raghav Sharma --- arch/arm64/boot/dts/exynos/exynos8855.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos8855.dtsi b/arch/arm64/boot/dts/exynos/exynos8855.dtsi index b461de6a7548..3dd7a4c4c609 100644 --- a/arch/arm64/boot/dts/exynos/exynos8855.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8855.dtsi @@ -241,6 +241,27 @@ pinctrl_pericmmc: pinctrl@154f0000 { interrupts = ; }; + cmu_hsi: clock-controller@17000000 { + compatible = "samsung,exynos8855-cmu-hsi"; + reg = <0x17000000 0x10000>; + #clock-cells = <1>; + + clocks = <&oscclk>, + <&cmu_top CLKCMU_DOUT_HSI_NOC>, + <&cmu_top CLKCMU_DOUT_HSI_UFS_EMBD>; + clock-names = "oscclk", + "bus", + "ufs_embd"; + samsung,sysreg = <&sysreg_hsi>; + }; + + sysreg_hsi: syscon@17020000 { + compatible = "samsung,exynos8855-hsi-sysreg", + "syscon"; + reg = <0x17020000 0x10000>; + clocks = <&cmu_hsi CLK_GOUT_SYSREG_HSI>; + }; + pinctrl_hsi_ufs: pinctrl@17040000 { compatible = "samsung,exynos8855-pinctrl"; reg = <0x17040000 0x1000>; -- 2.34.1