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From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
To: Ryan Brue <ryanbrue.dev@gmail.com>
Cc: Chen-Yu Tsai <wenst@chromium.org>,
	Mark Brown <broonie@kernel.org>, Lee Jones <lee@kernel.org>,
	Arnd Bergmann <arnd@arndb.de>, Sean Wang <sean.wang@kernel.org>,
	Linus Walleij <linusw@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	Bartosz Golaszewski <brgl@kernel.org>,
	Clark Williams <clrkwllms@kernel.org>,
	Steven Rostedt <rostedt@goodmis.org>,
	Yingjoe Chen <yingjoe.chen@mediatek.com>,
	Chaotian Jing <chaotian.jing@mediatek.com>,
	Hongzhou Yang <hongzhou.yang@mediatek.com>,
	linux-mediatek@lists.infradead.org, linux-gpio@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-rt-devel@lists.linux.dev, mfd@lists.linux.dev
Subject: Re: [PATCH] pinctrl: mediatek: common-v1: Use a raw spinlock for the pinctrl regmap
Date: Tue, 20 Oct 2026 09:32:36 +0200	[thread overview]
Message-ID: <20261020073236.dDVmd3BW@linutronix.de> (raw)
In-Reply-To: <d3d3e7b3-eb8b-456d-9a2c-116334e86c14@gmail.com>

On 2026-10-06 19:57:01 [-0500], Ryan Brue wrote:
> Hi Chen-Yu and Sebastian,
> 
> Thanks for looking at this.
> 
> On 9/30/26 3:17 AM, Chen-Yu Tsai wrote:
> > The syscon node is the provider of the regmap. You need to fix it there,
> > not duplicate it in the consumer.
> 
> Unless I'm misunderstanding, no driver binds to that node, so its regmap
> comes from the generic syscon code, and changing it there would affect every
> syscon. Lee, Arnd, Mark, would that be acceptable?
> 
> These are the options I see. Please let me know if there's a better one:
> 
> - Do what Sebastian suggested and make syscon use a raw spinlock, except
> when the node has a clock, since regmap-mmio calls clk_enable() under the
> lock. Off PREEMPT_RT, nothing changes. On RT the lock would no longer be
> preemptible for most syscons, including across bulk writes. Most syscon
> users that do bulk writes only write a few registers, but enabling the
> Amlogic G12A PCIe PLL writes a sequence with 40 us of udelay() under the
> lock.

bulk writes could be a concern. The 40us delay is within the lock
acquired? If so, could this be done without the lock? I assume this is
part of the init sequence so nothing should use the HW so the writes
should not be interrupted by other writes to the device.

> - Have the pinctrl ioremap() the node a second time alongside syscon's
> mapping and read the input register (DIN) with readl(). That read is the
> only access the EINT code makes in raw context. This would go around the
> syscon, and it requires that DIN never be written in a multi-step sequence,
> which is currently the case.

So it would be safe for now…

> I'd like to know the best approach before sending out a v2.
> 
> Best regards,
> Ryan Brue

Sebastian

      reply	other threads:[~2026-10-20  7:32 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-29 17:57 Ryan Brue
2026-09-29 18:09 ` sashiko-bot
2026-09-30  8:06 ` Sebastian Andrzej Siewior
2026-09-30  8:17   ` Chen-Yu Tsai
2026-10-07  0:57     ` Ryan Brue
2026-10-20  7:32       ` Sebastian Andrzej Siewior [this message]

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