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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ad8030226csm1079181a91.12.2026.10.20.13.47.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2026 13:47:53 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 05/12] drm/msm/a8xx: Stop getting GMEM_PROTECT from nonctx list Date: Tue, 20 Oct 2026 13:46:19 -0700 Message-ID: <20261020204728.28844-6-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261020204728.28844-1-robin.clark@oss.qualcomm.com> References: <20261020204728.28844-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIwMDA4MiBTYWx0ZWRfX2Y211m6dKyiw RdgU7PMv7ah3YjSa7vZG72ehdUX5WANM5Fn+6U1ATx7Xhs0FejOsVy/WyfNuNOPPHpvHywcn9tG mLUnneAy6Jpb/J0whRnJsFWJjwaZmMV9zOzyLn3hTgoaQ/3OFf2wzWMmUTFPw+6AriAAEag0Dg/ AdQgzwYXM7g1PjJQc6E2a9C3ZNHhxXXJZ0CrJ3i58BNPDh06z/nMEKKiogIuxwLpYyS7oANsoZP 4o0ySFdO5V1kAHr4FbjLOw+3KaEGW5ww1L0x+bSxPXNTBsPu64pQJvB9Kh3ABzI6VxiZDgXmSfO yS0yjHNMB7a/BIb4a2Yq6tQ4JKi2QlVjuiBp/FleJDfKeSDLKqq/WFC4VdxYcc2xKXkCrnyCx0N +ui0ocWvWjerQaTzAipGeIfWE5xKgjWZvP180XGve6tEw7XjHuz1ogHZMqUaFJF3zbJxBmf68+F iBO4ZHkMGbBncssXlzw== X-Proofpoint-ORIG-GUID: zG3irG0ud5KO0YbPcI5mLYdeZHUXYVlu X-Proofpoint-GUID: zG3irG0ud5KO0YbPcI5mLYdeZHUXYVlu X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIwMDA4MiBTYWx0ZWRfX9gZ1I3lRTcEW ccH4aqbRZACPUqCP/X4clvAbuJb9n4naD6B+kQk99Z/4QDdgtpNO06PSsf4vo8S7XKvSZxgANr3 6dg/Fs6P6NQGtY42Ur12LrmbEL5WSwo= X-Authority-Analysis: v=2.4 cv=NppE4MdJ c=1 sm=1 tr=0 ts=6ad7d37a cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=b4MSL0WmfgirtTH71F4A:9 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-20_03,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610200082 We can just simplify things and calculate the value, instead of manually adding it to the nonctx list. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index 3e22ef788f2d..6d7982a117f7 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -373,7 +373,7 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) hbb_lo << 1 | ubwc_mode); } -static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) +static void a8xx_nonctxt_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gmu *gmu = &to_a6xx_gpu(adreno_gpu)->gmu; @@ -393,9 +393,6 @@ static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) if (!(BIT(pipe_id) & regs[i].pipe)) continue; - if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT) - *gmem_protect = regs[i].value; - if ((regs[i].offset << 2) >= gmu->mmio_offset) { gmu_write(gmu, regs[i].offset, regs[i].value); } else { @@ -641,7 +638,6 @@ static int hw_init(struct msm_gpu *gpu) struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu = &a6xx_gpu->gmu; unsigned int pipe_id, i; - u32 gmem_protect = 0; u64 gmem_range_min; int ret; @@ -722,7 +718,7 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A8XX_UCHE_CLIENT_PF, BIT(7) | 0x1); - a8xx_nonctxt_config(gpu, &gmem_protect); + a8xx_nonctxt_config(gpu); /* Enable fault detection */ gpu_write(gpu, REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, BIT(30) | 0xcfffff); @@ -841,8 +837,8 @@ static int hw_init(struct msm_gpu *gpu) * GMEM_PROTECT register should be programmed after GPU is transitioned to * non-secure mode */ - a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_GC_GMEM_PROTECT, gmem_protect); - WARN_ON(!gmem_protect); + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_GC_GMEM_PROTECT, + (adreno_gpu->info->gmem / SZ_4K) << 16); a8xx_aperture_clear(gpu); if (!a6xx_gpu->pwrup_reglist_emitted) { -- 2.56.0