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Wed, 21 Oct 2026 06:51:46 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36740cc848fsm7534332eec.13.2026.10.21.06.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 06:51:45 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Wed, 21 Oct 2026 19:21:24 +0530 Subject: [PATCH 3/3] arm64: dts: qcom: glymur-crd: Describe the PCIe M.2 Key B connector X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261021-pcie6_fix-v1-3-ad37134c35a3@oss.qualcomm.com> References: <20261021-pcie6_fix-v1-0-ad37134c35a3@oss.qualcomm.com> In-Reply-To: <20261021-pcie6_fix-v1-0-ad37134c35a3@oss.qualcomm.com> To: Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Bjorn Andersson , Konrad Dybcio Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, Krishna Chaitanya Chundru X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792590686; l=2234; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=N4sUA81o0uvR6JdRpINVUf4MY/Mr1oj/T6BQ1Wygh9o=; b=Mdyqv8Zf06NuraQphLE0x8nVr/anXhWSoGzD68/+GdqDV3SEHuXyw0N0AGK6CGE3tJDTk5X/X 0f1Bi/Acn5JCklLc75L4R3KL1umI5ACEtsxpwIhEWvgWEfm5OeQcGnm X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: 0fg72nIMvA-q0215X0PR85Q6pzh_taho X-Proofpoint-GUID: 0fg72nIMvA-q0215X0PR85Q6pzh_taho X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA1NSBTYWx0ZWRfXwW8yQVprX0HI muT9yoJZc2/+cjphXx2uwCTyH08QR4Nn+Rkyd1xST9u2//8Pp9YeembYm1jN88q+7oIFjLSHM5h IL0DICdcB76zOR4ATL7tvTN61LlbNnY= X-Authority-Analysis: v=2.4 cv=R7aWitRX c=1 sm=1 tr=0 ts=6ad8c373 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=bvY3E1ByFFb03tV5gjAA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA1NSBTYWx0ZWRfX2xGNN5DWop0C EpbIsj5c4nRe4wtqVC73bvZs4ddc9+4V3I4fAme1nFaiDGfFYNIn2B2xDQhCbV4NBDoxulfKEYo VM0IWqcd6dWzYQz++gcQPvEgfUnwht9pDuwyM3BQNCHBFGt5bs6pPmXvXisfcFy1uEJ+W7Nrp1B JE7idDbSPjtd6HciNDF9v546ohk4SgkXTdzGvgTklUo9IwS2qO8PTuNi0nQ2xoJ6Dwoeapp74r7 C0P1/kv2Dn8XVGVhriwp0AYyrvLAvzdfpI7ebssajdgVfiDVJNXlongjyfs4NIVN2ngC+vfScEV tECt3Ad1gHRA9C8QEUwoOv5pRp/kQ4skQnMkwY4VEv1jTfmQ6m95y8Srp/RY5gaSu0f4vzefcCT +y/MnexdNF8tbn00OF4mYMqawrJ907xX80rfA8LBm3ufrsxUL4I0Gt6ZkwBsJuKmTJS2oSUMdFu tm897TYLWm2TTzf8VNg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_03,2026-10-21_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 impostorscore=0 bulkscore=0 spamscore=0 suspectscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210055 The Glymur CRD has a WWAN M.2 slot connected to PCIe6. Currently the vreg_wwan supply is described directly on the PCIe6 host bridge. As a result, the supply follows the PCIe controller power state and is turned off when the controller is powered down, regardless of the requirements of the device connected to the slot. Move control of the WWAN supply to the generic pci-pwrctrl-slot/pwrseq-pcie-m2 framework. This allows slot power to be coordinated with PCI device power-management requirements and keeps the supply enabled when required by the PCI device, such as for PME-based wake-up. Describe the slot as a PCIe M.2 Mechanical Key B connector and link it to the PCIe6 Root Port using a graph port/endpoint pair, as required by the pcie-m2-b-connector binding. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 29 +++++++++++++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index e27c697e3170..73de60b0d0e5 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -237,6 +237,27 @@ vreg_wwan: regulator-wwan { pinctrl-names = "default"; }; + wwan-connector { + compatible = "pcie-m2-b-connector"; + vpcie3v3-supply = <&vreg_wwan>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + wwan_m2_pcie_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&pcie6_port0_ep>; + }; + }; + }; + }; + sound { compatible = "qcom,glymur-sndcard"; model = "GLYMUR-CRD"; @@ -810,8 +831,6 @@ &pcie5_port0 { }; &pcie6 { - vddpe-3v3-supply = <&vreg_wwan>; - pinctrl-0 = <&pcie6_default>; pinctrl-names = "default"; @@ -828,6 +847,12 @@ &pcie6_phy { &pcie6_port0 { reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>; + + port { + pcie6_port0_ep: endpoint { + remote-endpoint = <&wwan_m2_pcie_ep>; + }; + }; }; &pmh0110_f_e1_gpios { -- 2.34.1