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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4a7d61ce790sm2885699fac.11.2026.10.21.14.02.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 14:02:19 -0700 (PDT) From: James Hilliard Date: Wed, 21 Oct 2026 15:02:13 -0600 Subject: [PATCH] dmaengine: sun6i: use the channel pause enable bit X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261021-submit-sun6i-dma-pause-bit-v1-v1-1-38d286b69dab@gmail.com> X-B4-Tracking: v=1; b=H4sIAAAAAAAC/yWM2wqDMBBEf0X2uUtNChr6K6UPuWx1C24lUSmI/ 95NfRrOMHN2KJSZCtybHTJtXPgjCubSQBy9DISclMG2tjOtNVjWMPGiIR1jmjzOfi2EQbvNYGd cNPHm+j45UMec6cXfv//xPFkFb4pLldZF8PWdvcSxVmokGVjoev6O4wcRv+NjowAAAA== X-Change-ID: 20261021-submit-sun6i-dma-pause-bit-v1-618c1c3877d8 To: Vinod Koul , Frank Li , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , Arnd Bergmann Cc: dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, James Hilliard X-Mailer: b4 0.15.2 The channel pause register uses bit 0 to suspend DMA requests. Bit 1 is reserved, but sun6i_dma_pause() writes only that bit and returns success. An active peripheral transfer can therefore continue while its client expects it to be paused, for example while the 8250 driver reads RX residue and copies a partially filled receive buffer. Use bit 0, as specified by the H616 DMA channel pause register. This fixes the pause request itself; it does not add paused-state reporting or change the handling of transactions already on the bus. Fixes: 555859308723 ("dmaengine: sun6i: Add driver for the Allwinner A31 DMA controller") Signed-off-by: James Hilliard --- drivers/dma/sun6i-dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c index 7704b016aed8..204b0b812431 100644 --- a/drivers/dma/sun6i-dma.c +++ b/drivers/dma/sun6i-dma.c @@ -60,7 +60,7 @@ #define DMA_CHAN_ENABLE_STOP 0 #define DMA_CHAN_PAUSE 0x04 -#define DMA_CHAN_PAUSE_PAUSE BIT(1) +#define DMA_CHAN_PAUSE_PAUSE BIT(0) #define DMA_CHAN_PAUSE_RESUME 0 #define DMA_CHAN_LLI_ADDR 0x08 --- base-commit: 93f51579e7df248780214094418f205253383cc5 change-id: 20261021-submit-sun6i-dma-pause-bit-v1-618c1c3877d8 Best regards, -- James Hilliard