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Tue, 20 Oct 2026 21:20:41 -0700 (PDT) Received: from AERO17.taila7786d.ts.net ([152.175.65.42]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8a08933aec9sm318936b3a.2.2026.10.20.21.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2026 21:20:39 -0700 (PDT) From: Pufan Jin To: Andrew Lunn , Heiner Kallweit , Russell King Cc: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next v3] net: phy: realtek: Add support for JLSemi JL2101 and JL2121 PHYs Date: Wed, 21 Oct 2026 12:20:29 +0800 Message-ID: <20261021042029.44853-1-cyan2254650260@gmail.com> X-Mailer: git-send-email 2.56.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit JLSemi (JingLue Semiconductor) JL2101 and JL2121 Gigabit Ethernet PHYs are register-compatible second-source alternatives to the Realtek RTL8211F. They share the same paged register layout (page select at register 0x1f), RGMII TX/RX internal delay registers (page 0xd08 regs 11/15), and specific status register (0x1a). Wake-on-LAN (WoL) events (page 0xd8a regs 16/17 and page 0xd8c reg 16) and LED control registers (page 0xd04 reg 0x10) match RTL8211F. Unlike RTL8211F where PHYSR (0x1a) can be read directly on page 0, JL2101/JL2121 requires reading PHYSR from page 0xa43 via phy_read_paged(). Reading 0x1a on page 0 yields 0x0000, which causes rtlgen_decode_physr() to erroneously downshift to 10Mbps half duplex. Introduce jlsemi_read_status() to read PHYSR with page 0xa43. Extend the Realtek PHY driver to bind JL2101 and JL2121 by their PHY IDs to the RTL8211F-compatible driver operations, and add their PHY IDs to the MDIO module device table. Signed-off-by: Pufan Jin --- Changes in v3: - Drop standalone driver drivers/net/phy/jlsemi.c and extend the Realtek PHY driver directly as suggested by Andrew Lunn. - Add jlsemi_read_status() to read PHYSR (0x1a) via phy_read_paged() from page 0xa43, avoiding false downshift to 10Mbps half duplex (verified on physical ALINX AX7Z020B board). Changes in v2: - Drop redundant phy_interface_is_rgmii() check in jlsemi_config_init() (Andrew Lunn) - Change speed check in jlsemi_read_status() to '>= SPEED_1000' since JL21xx only supports up to 1000M and 100BASE-TX does not use Master/Slave clock resolution (Andrew Lunn) - Check device_can_wakeup() and configure wakeup capability and wake IRQ in probe() when 'wakeup-source' is present (Andrew Lunn) - Drop redundant .features = PHY_GBIT_FEATURES (Andrew Lunn) - Use PHY_ID_MATCH_VENDOR() for generic driver and mdio table (Andrew Lunn) drivers/net/phy/realtek/realtek_main.c | 61 ++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/net/phy/realtek/realtek_main.c b/drivers/net/phy/realtek/realtek_main.c index 177b62a7b..36c8f2529 100644 --- a/drivers/net/phy/realtek/realtek_main.c +++ b/drivers/net/phy/realtek/realtek_main.c @@ -259,6 +259,10 @@ #define RTL_8261C 0x001cc890 #define RTL_8261C_CG 0x001cc898 +#define JLSEMI_JL2101_PHYID 0x937c4032 +#define JLSEMI_JL2121_PHYID 0x937c4030 +#define JLSEMI_STATUS_PAGE 0xa43 + #define RTL8261C_CE_MODEL 0x00 #define RTL8261D_MODEL 0x81 #define RTL8261X_INT_AUTONEG_ERROR BIT(0) @@ -1731,6 +1735,23 @@ static int rtlgen_read_status(struct phy_device *phydev) return 0; } +static int jlsemi_read_status(struct phy_device *phydev) +{ + int ret, val; + + ret = genphy_read_status(phydev); + if (ret < 0 || !phydev->link) + return ret; + + val = phy_read_paged(phydev, JLSEMI_STATUS_PAGE, RTL_PHYSR); + if (val < 0) + return val; + + rtlgen_decode_physr(phydev, val); + + return 0; +} + static int rtlgen_read_vend2(struct phy_device *phydev, int regnum) { return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); @@ -3192,6 +3213,44 @@ static struct phy_driver realtek_drvs[] = { .led_hw_control_get = rtl8211f_led_hw_control_get, .led_hw_control_set = rtl8211f_led_hw_control_set, .disable_autonomous_eee = rtl8211f_disable_autonomous_eee, + }, { + PHY_ID_MATCH_EXACT(JLSEMI_JL2101_PHYID), + .name = "JLSemi JL2101 Gigabit Ethernet", + .probe = rtl8211f_probe, + .config_init = &rtl8211f_config_init, + .read_status = jlsemi_read_status, + .config_intr = &rtl8211f_config_intr, + .handle_interrupt = rtl8211f_handle_interrupt, + .set_wol = rtl8211f_set_wol, + .get_wol = rtl8211f_get_wol, + .suspend = rtl8211f_suspend, + .resume = rtl8211f_resume, + .read_page = rtl821x_read_page, + .write_page = rtl821x_write_page, + .flags = PHY_ALWAYS_CALL_SUSPEND, + .led_hw_is_supported = rtl8211x_led_hw_is_supported, + .led_hw_control_get = rtl8211f_led_hw_control_get, + .led_hw_control_set = rtl8211f_led_hw_control_set, + .disable_autonomous_eee = rtl8211f_disable_autonomous_eee, + }, { + PHY_ID_MATCH_MODEL(JLSEMI_JL2121_PHYID), + .name = "JLSemi JL2121 Gigabit Ethernet", + .probe = rtl8211f_probe, + .config_init = &rtl8211f_config_init, + .read_status = jlsemi_read_status, + .config_intr = &rtl8211f_config_intr, + .handle_interrupt = rtl8211f_handle_interrupt, + .set_wol = rtl8211f_set_wol, + .get_wol = rtl8211f_get_wol, + .suspend = rtl8211f_suspend, + .resume = rtl8211f_resume, + .read_page = rtl821x_read_page, + .write_page = rtl821x_write_page, + .flags = PHY_ALWAYS_CALL_SUSPEND, + .led_hw_is_supported = rtl8211x_led_hw_is_supported, + .led_hw_control_get = rtl8211f_led_hw_control_get, + .led_hw_control_set = rtl8211f_led_hw_control_set, + .disable_autonomous_eee = rtl8211f_disable_autonomous_eee, }, { .name = "Generic FE-GE Realtek PHY", .match_phy_device = rtlgen_match_phy_device, @@ -3420,6 +3479,8 @@ module_phy_driver(realtek_drvs); static const struct mdio_device_id __maybe_unused realtek_tbl[] = { { PHY_ID_MATCH_VENDOR(0x001cc800) }, + { PHY_ID_MATCH_EXACT(JLSEMI_JL2101_PHYID) }, + { PHY_ID_MATCH_MODEL(JLSEMI_JL2121_PHYID) }, { } }; -- 2.56.0