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Tue, 20 Oct 2026 23:00:55 -0700 (PDT) Received: from john-desktop.station ([109.77.5.121]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a1fb83ff0dsm63793845e9.7.2026.10.20.23.00.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2026 23:00:54 -0700 (PDT) From: John O'Callaghan To: Chuan Liu Cc: Neil Armstrong , Jerome Brunet , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl , linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 2/4] clk: amlogic: Improve the issue of PLL lock failures Date: Wed, 21 Oct 2026 06:59:25 +0100 Message-ID: <20261021060005.2947837-1-johnocallaghan@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20251031-optimize_pll_driver-v3-2-92f3b2f36a83@amlogic.com> References: <20251031-optimize_pll_driver-v3-0-92f3b2f36a83@amlogic.com> <20251031-optimize_pll_driver-v3-2-92f3b2f36a83@amlogic.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Chuan, Jerome asked what was tested; here is a G12A data point. On a Radxa Zero (S905Y2, G12A) running v7.3, sys_pll_dco occasionally fails to lock on cpufreq transitions, at room temperature: meson_clk_pll_set_rate: pll sys_pll_dco didn't lock, trying to set old rate 6000000000 It happens with all the sys_pll OPPs (old DCO rates 3216, 3408, 3600, 4800, 5592 and 6000 MHz) but, here, only while the video decoder is busy. Reproducer: the userspace governor, random writes of the 1200-1800 MHz OPPs to scaling_setspeed (~700 transitions/s), with a GStreamer v4l2 decode loop (meson vdec, H.264 + VP9 1080p) running alongside. 46 C SoC temperature. transitions lock failures v7.3 500290 33 v7.3, no decoder running 250056 0 v7.3 + this series (1-4) 500089 0 v7.3 + patch 2/4 only 500066 0 So on G12A it is the 20 us delays of this patch that make the difference. Tested-by: John O'Callaghan # Radxa Zero (G12A) The testing was scripted with the help of an LLM coding assistant; I ran it on my board and checked the results. Thanks, John