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Tue, 20 Oct 2026 23:14:53 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , , , , , , , , , , Subject: [PATCH v2 09/10] PCI: tegra194: Balance core monitor clock on failures Date: Wed, 21 Oct 2026 11:43:48 +0530 Message-ID: <20261021061349.1265704-10-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261021061349.1265704-1-mmaddireddy@nvidia.com> References: <20261021061349.1265704-1-mmaddireddy@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|IA0PR12MB8747:EE_ X-MS-Office365-Filtering-Correlation-Id: a91f0c53-bc82-415f-570a-08df2f3aaa1b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|7416014|1800799024|376014|36860700016|82310400026|56012099006|11063799006|261009223027099003|10067099003|18002099003|22082099003; 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The enable error is also only logged, so later cleanup can try to disable a clock that was never enabled. Track the monitor clock state, return enable failures, and use a common helper on retry, remove, suspend, shutdown and host-init failure paths so the clock is disabled exactly when it was enabled. Fixes: a86ca8698c88 ("PCI: tegra194: Add core monitor clock support") Signed-off-by: Manikanta Maddireddy --- Changes V1 -> V2: None drivers/pci/controller/dwc/pcie-tegra194.c | 33 ++++++++++++++++++---- 1 file changed, 27 insertions(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index de14a23f9a4d..632ecab3c8ea 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -246,6 +246,7 @@ struct tegra_pcie_dw { void __iomem *appl_base; struct clk *core_clk; struct clk *core_clk_m; + bool core_clk_m_enabled; struct reset_control *core_apb_rst; struct reset_control *core_rst; struct dw_pcie pci; @@ -855,6 +856,15 @@ static void tegra_pcie_enable_interrupts(struct dw_pcie_rp *pp) tegra_pcie_enable_msi_interrupts(pp); } +static void tegra_pcie_disable_core_clk_m(struct tegra_pcie_dw *pcie) +{ + if (!pcie->core_clk_m_enabled) + return; + + clk_disable_unprepare(pcie->core_clk_m); + pcie->core_clk_m_enabled = false; +} + static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie) { struct dw_pcie *pci = &pcie->pci; @@ -914,6 +924,7 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); u32 val; u16 val_16; + int ret; pp->bridge->ops = &tegra_pci_ops; @@ -965,8 +976,12 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) } clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); - if (clk_prepare_enable(pcie->core_clk_m)) - dev_err(pci->dev, "Failed to enable core monitor clock\n"); + ret = clk_prepare_enable(pcie->core_clk_m); + if (ret) { + dev_err(pci->dev, "Failed to enable core monitor clock: %d\n", ret); + return ret; + } + pcie->core_clk_m_enabled = true; return 0; } @@ -1049,8 +1064,11 @@ static int tegra_pcie_dw_start_link(struct dw_pcie *pci) * dw_pcie_host_init(). Disable the clock since below * tegra_pcie_dw_host_init() will enable it again. */ - clk_disable_unprepare(pcie->core_clk_m); - tegra_pcie_dw_host_init(pp); + tegra_pcie_disable_core_clk_m(pcie); + ret = tegra_pcie_dw_host_init(pp); + if (ret) + return ret; + dw_pcie_setup_rc(pp); retry = false; @@ -1565,6 +1583,7 @@ static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie) return 0; fail_host_init: + tegra_pcie_disable_core_clk_m(pcie); tegra_pcie_unconfig_controller(pcie); return ret; } @@ -1653,7 +1672,7 @@ static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie) static void tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie) { - clk_disable_unprepare(pcie->core_clk_m); + tegra_pcie_disable_core_clk_m(pcie); dw_pcie_host_deinit(&pcie->pci.pp); tegra_pcie_dw_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); @@ -2451,7 +2470,7 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev) if (!pcie->link_state) return 0; - clk_disable_unprepare(pcie->core_clk_m); + tegra_pcie_disable_core_clk_m(pcie); tegra_pcie_dw_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); @@ -2488,6 +2507,7 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev) return 0; fail_host_init: + tegra_pcie_disable_core_clk_m(pcie); tegra_pcie_unconfig_controller(pcie); return ret; } @@ -2529,6 +2549,7 @@ static void tegra_pcie_dw_shutdown(struct platform_device *pdev) if (IS_ENABLED(CONFIG_PCI_MSI)) disable_irq(pcie->pci.pp.msi_irq[0]); + tegra_pcie_disable_core_clk_m(pcie); tegra_pcie_dw_pme_turnoff(pcie); tegra_pcie_unconfig_controller(pcie); pm_runtime_put_sync(pcie->dev); -- 2.34.1