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Tue, 20 Oct 2026 23:14:58 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , , , , , , , , , , Subject: [PATCH v2 10/10] PCI: tegra194: Reject zero MSI interrupt number Date: Wed, 21 Oct 2026 11:43:49 +0530 Message-ID: <20261021061349.1265704-11-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261021061349.1265704-1-mmaddireddy@nvidia.com> References: <20261021061349.1265704-1-mmaddireddy@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: EA8PEPF00000008:EE_|DS6PR12MB500340:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d400828-ef08-461b-d6b4-08df2f3ab157 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|7416014|23010399003|1800799024|22082099003|18002099003|10067099003|261009223027099003|11063799006|56012099006; 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The endpoint IRQ API uses interrupt numbers in the range 1-N, and existing EPF drivers already follow that convention. This is defensive validation rather than a correction to the MSI numbering used by those drivers. Signed-off-by: Manikanta Maddireddy --- Changes V1 -> V2: - Retain only MSI interrupt-number-zero validation from v1 patch 10. - Rewrite the title and commit message around defensive MSI validation, and remove the Fixes tag. drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 632ecab3c8ea..0f49ea6df8bc 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -2026,7 +2026,7 @@ static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq) static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq) { - if (unlikely(irq > 32)) + if (unlikely(!irq || irq > 32)) return -EINVAL; appl_writel(pcie, BIT(irq - 1), APPL_MSI_CTRL_1); -- 2.34.1