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Tue, 20 Oct 2026 23:14:42 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , , , , , , , , , , Subject: [PATCH v2 07/10] PCI: tegra194: Always disable Tegra234 Endpoint L1.2 Date: Wed, 21 Oct 2026 11:43:46 +0530 Message-ID: <20261021061349.1265704-8-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261021061349.1265704-1-mmaddireddy@nvidia.com> References: <20261021061349.1265704-1-mmaddireddy@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: EA8PEPF00000008:EE_|SN7PR12MB7228:EE_ X-MS-Office365-Filtering-Correlation-Id: c018a57c-136f-44e8-21de-08df2f3aa94f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|23010399003|36860700016|1800799024|82310400026|56012099006|11063799006|261009223027099003|10067099003|22082099003|18002099003|6133799003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: XTCJ33VjkRPPBop6yhnV3EUSIL6trlLo0LHRqxvlDvnOJ3wN6XOVD2UstqjUG4jVFpSHo7hmXQuRpxxC5ydB4NRb0XoHJWrgehejZYRyvX9txfPgRss70VrZ7XtAvHFgyaC7tuJ8RBpCKXRQcBC9hd3gsrKq70jI7r0RiS8ohscWKU+W7HMMhfr3aaWJ5bKQYHA3ax1voFlmYFhoUovVQKMJZi6+gEAnG5IlIUOMAisVu6QBNQj0e7ZM7SNtpkulWj/5rrBZ+7sNWb8ycptwBdx2tXHq54hvr05Zy+PRXwxgPnQOdKYjTDONE7Ztlif6Q+Mr1a7Lkuq+538Q3pYkw76vlJKVkgR/rfZnWymd/42HcutaHAoL8MuLD/AFCQOGpAK5LqCZRXnFN9gPepTmRlW/OU+FWUvGpgSfXvUglSsXcQBaZ8I1zA/RbzHkXCEY X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2026 06:15:10.3666 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c018a57c-136f-44e8-21de-08df2f3aa94f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: EA8PEPF00000008.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7228 Tegra234 Endpoint mode must not advertise L1.2 because exiting L1.2 can bring the link down. That hardware workaround is required regardless of whether the endpoint kernel is built with CONFIG_PCIEASPM. Move the L1.2 capability masking out of init_host_aspm(), which is compiled out when CONFIG_PCIEASPM is disabled, and apply it from the common initialization paths. Fixes: f59df1d9e6bd ("PCI: tegra194: Disable L1.2 capability of Tegra234 EP") Signed-off-by: Manikanta Maddireddy --- Changes V1 -> V2: None drivers/pci/controller/dwc/pcie-tegra194.c | 47 +++++++++++++--------- 1 file changed, 28 insertions(+), 19 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 7c349478556d..0e6224b6751d 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -611,6 +611,33 @@ static struct pci_ops tegra_pci_ops = { .write = tegra_pcie_dw_wr_own_conf, }; +/* + * Disable L1.2 capability advertisement for Tegra234 Endpoint mode. + * Tegra234 has a hardware bug where during L1.2 exit, the UPHY PLL is + * powered up immediately without waiting for REFCLK to stabilize. This causes + * the PLL to fail to lock to the correct frequency, resulting in PCIe link + * loss. Since there is no hardware fix available, prevent the Endpoint from + * advertising L1.2 support so the host will not attempt to enter L1.2 with + * this Endpoint. + */ +static void tegra_pcie_disable_ep_l1_2(struct tegra_pcie_dw *pcie) +{ + struct dw_pcie *pci = &pcie->pci; + u32 l1ss, val; + + if (!pcie->of_data->disable_l1_2 || + pcie->of_data->mode != DW_PCIE_EP_TYPE) + return; + + l1ss = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); + if (!l1ss) + return; + + val = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP); + val &= ~(PCI_L1SS_CAP_PCIPM_L1_2 | PCI_L1SS_CAP_ASPM_L1_2); + dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, val); +} + #if defined(CONFIG_PCIEASPM) static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event) { @@ -694,25 +721,6 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie) if (pcie->supports_clkreq) pci->l1ss_support = true; - - /* - * Disable L1.2 capability advertisement for Tegra234 Endpoint - * mode. Tegra234 has a hardware bug where during L1.2 exit, - * the UPHY PLL is powered up immediately without waiting for - * REFCLK to stabilize. This causes the PLL to fail to lock to - * the correct frequency, resulting in PCIe link loss. Since - * there is no hardware fix available, prevent the Endpoint - * from advertising L1.2 support by clearing the L1.2 bits in - * the L1 PM Substates Capabilities register. This ensures the - * host will not attempt to enter L1.2 with this Endpoint. - */ - if (pcie->of_data->disable_l1_2 && - pcie->of_data->mode == DW_PCIE_EP_TYPE) { - val = dw_pcie_readl_dbi(pci, l1ss + PCI_L1SS_CAP); - val &= ~(PCI_L1SS_CAP_PCIPM_L1_2 | - PCI_L1SS_CAP_ASPM_L1_2); - dw_pcie_writel_dbi(pci, l1ss + PCI_L1SS_CAP, val); - } } /* Program L0s and L1 entrance latencies */ @@ -1903,6 +1911,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) config_gen3_gen4_eq_presets(pcie); init_host_aspm(pcie); + tegra_pcie_disable_ep_l1_2(pcie); if (!pcie->of_data->has_l1ss_exit_fix) { val = dw_pcie_readl_dbi(pci, GEN3_CTRL); -- 2.34.1