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Tue, 20 Oct 2026 23:14:47 -0700 From: Manikanta Maddireddy To: , , , , CC: , , , , , , , , , , , , Subject: [PATCH v2 08/10] PCI: tegra194: Guard Endpoint PLL-off error path Date: Wed, 21 Oct 2026 11:43:47 +0530 Message-ID: <20261021061349.1265704-9-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261021061349.1265704-1-mmaddireddy@nvidia.com> References: <20261021061349.1265704-1-mmaddireddy@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: EA8PEPF0000000B:EE_|IA3PR12MB773567:EE_ X-MS-Office365-Filtering-Correlation-Id: 714b3f1b-ab70-4c34-2986-08df2f3aabb6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|376014|7416014|23010399003|1800799024|6133799003|22082099003|18002099003|10067099003|261009223027099003|11063799006|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ktf/5BrQO69/aYwNnvrHjxcSpixmiLV2EPK45KJN7tV+IOGFbTwCZbSe9I24IUvW8q8ku2SGKce0NB12afNSWu9wRezb2tRzE5eOSKXZS3dMFSDcErLCGFkn3Hxz4DRcqaRc3v2EAXPx9COvS1oqTUL7vL/eLBMvutC059xp2Wg4ue3FvoBHuY8mTZJkqXSUHjfbgKj0x4tRiFxz5KelzSQDWw+nzPFan4B0l2mcWXSoRwkpP+DzY0r/Vqsp8y6LGAkW8VYryKSYLm9DgIeU7lI9lkKVX+TVCua/+4iELpjOb9hDxhx8qIO92I1pA6X3yZi0M1Bvr927UMglya7+xKEfqH0nIdLkFxsupdIa1uDmVmPq8THsqcdLnT6slYH+NNjTSPRgbUa255rqB4jrDSFMDsUgkAVf3ofIvARkUcR2UkW5wzwkspInp3osptlL X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2026 06:15:14.4406 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 714b3f1b-ab70-4c34-2986-08df2f3aabb6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: EA8PEPF0000000B.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA3PR12MB773567 The Endpoint PERST# deassert path initializes the external-refclk PLL only when enable_ext_refclk is set, but the error unwind always sent the PLL-off request. Guard the PLL-off request with enable_ext_refclk so Tegra234 Endpoint configurations that did not enable the PLL do not send a spurious BPMP PLL-off command. Fixes: a54e19073718 ("PCI: tegra194: Add Tegra234 PCIe support") Signed-off-by: Manikanta Maddireddy --- Changes V1 -> V2: None drivers/pci/controller/dwc/pcie-tegra194.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 0e6224b6751d..de14a23f9a4d 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1973,7 +1973,8 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) fail_core_apb_rst: clk_disable_unprepare(pcie->core_clk); fail_core_clk_enable: - tegra_pcie_bpmp_set_pll_state(pcie, false); + if (pcie->enable_ext_refclk) + tegra_pcie_bpmp_set_pll_state(pcie, false); fail_pll_init: tegra_pcie_bpmp_set_ctrl_state(pcie, false); fail_set_ctrl_state: -- 2.34.1