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Tue, 20 Oct 2026 23:19:16 -0700 From: Manikanta Maddireddy To: , , , , , CC: , , , , , , , Subject: [PATCH v2 0/3] PCI: dwc: Avoid full EP cleanup on PERST# Date: Wed, 21 Oct 2026 11:49:00 +0530 Message-ID: <20261021061903.1269605-1-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A9:EE_|LV2PR12MB539562:EE_ X-MS-Office365-Filtering-Correlation-Id: a43a5afd-571c-4f36-5bac-08df2f3b4bb9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|23010399003|36860700016|56012099006|5023799004|11063799006|261009223027099003|10067099003|18002099003|6133799003|13003099007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 8rimpvNVMhWeVcDGndsIYOh8eMuS/bfGOFtDxxTF3fs+rkh/2NTWDZlDwp7/6VXpozW5+u0386wFAZiunCMLi5YRMtwbFOxS/GKoXM0DYoE+RV4aGv8ZJG1Ja4lc/FGbiT9OqoFnRr1/3JZO0mzMOc91N4OFeW08ez40hx8JD0GLs7q3clXSAPNnw3KhsDOnZ8dDSw9K8EyLYdMq+BPQjgUybZs6SNY8ORHIAU5lDWyCkhMW6Unsf/OrZKPrPPBPYR4/AuWi2o8AFjhZOGJaG5bCmmPFhKCxrMjW+Ioxnlhh5R6RZm5XO4MpwxmzheV2bhPbuLsr/zabklKGPxdqzwCn+JVdYYkVvEGWg5knpFdh7s2feV7U21wDslsCvRYYhs3fdvgDtOAlaRzXvpQ2gd0ih8TkF54rTC3VXM/tTJ2YHMMYZO6leGm6QG4I3moG X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2026 06:19:42.8116 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a43a5afd-571c-4f36-5bac-08df2f3b4bb9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF000044A9.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB539562 This series avoids repeating full DWC Endpoint software resource cleanup and initialization on every PERST# cycle while still restoring reset-lost hardware state on the following PERST# deassertion. The current Tegra194/234 Endpoint flow runs the full DWC EP cleanup/init sequence for each PERST# cycle. The allocation bitmaps, outbound-address array and per-function descriptors already have allocation guards and can be reused. Repeated full cleanup/init also removes and recreates debugfs entries and unregisters and reprobes eDMA where present; eDMA detection allocates managed linked-list memory retained until device detach. Patch 1 folds initial setup and reset recovery into the existing dw_pcie_ep_init_registers() API. It tracks successful resource setup and uses a private helper to restore reset-lost registers on subsequent calls. After hardware resets the iATU, cached outbound mapping state is reset so stale bookkeeping does not hide available windows. This does not disable or unmap live hardware windows. Patch 2 removes the full DWC EP cleanup from Tegra PERST# deassertion, allowing the existing initialization API to retain software resources and restore registers. Patch 3 notifies EPFs of link down before powering off the controller on PERST# assertion, allowing their callbacks to quiesce work. It calls pci_epc_linkdown() directly to avoid the DWC linkdown helper's DBI register reinitialization after REFCLK may have disappeared. EPF callbacks can still access MMIO; the notification is not a guarantee of register-free execution. Hardware-dependent EPF deinitialization remains in the PERST# deassert path where REFCLK is available and core reset has been deasserted. This series is prepared on top of the v2 Tegra Endpoint/Root Port corner-case fixes and the preceding DWC register-field cleanup series. Changes in v2: - Rename the outbound helper to dw_pcie_ep_reset_outbound_state() and clarify that it invalidates software state after hardware reset rather than disabling live iATU mappings. - Fold init/reinit selection into dw_pcie_ep_init_registers(). Remove the separate init-or-reinit API and keep register restoration private. - Document the reset and quiescence prerequisites and retain full initialization after dw_pcie_ep_cleanup() clears the resource-state flag. - Clarify which resources are retained and avoid implying that the existing guarded allocations were repeated on every reset. - Keep Tegra's existing initialization call; only remove per-reset cleanup. - Narrow the linkdown notification's safety claim and remove unrelated pointer cleanup and teardown discussion from patch 3. - Reword the resource-lifetime explanations in patches 1 and 2. Validation: - ARM64 compilation of the DWC EP, host, core and Tegra objects passed. - Per-patch checkpatch and whitespace checks passed. - Verified Endpoint reset sequence multiple times. - Verified ./pci_endpoint_test tests after Endpoint reset sequence. v1: https://lore.kernel.org/linux-pci/20260923072554.1141864-1-mmaddireddy@nvidia.com/ Manikanta Maddireddy (3): PCI: dwc: Reuse Endpoint resources after fundamental reset PCI: tegra194: Avoid full Endpoint reinit on PERST# PCI: tegra194: Notify Endpoint functions on PERST# assert .../pci/controller/dwc/pcie-designware-ep.c | 149 +++++++++++++----- drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/controller/dwc/pcie-tegra194.c | 4 +- 3 files changed, 111 insertions(+), 43 deletions(-) -- 2.34.1