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Tue, 20 Oct 2026 23:19:20 -0700 From: Manikanta Maddireddy To: , , , , , CC: , , , , , , , Subject: [PATCH v2 1/3] PCI: dwc: Reuse Endpoint resources after fundamental reset Date: Wed, 21 Oct 2026 11:49:01 +0530 Message-ID: <20261021061903.1269605-2-mmaddireddy@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261021061903.1269605-1-mmaddireddy@nvidia.com> References: <20261021061903.1269605-1-mmaddireddy@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A6:EE_|DS0PR12MB8270:EE_ X-MS-Office365-Filtering-Correlation-Id: 4e29813a-115b-4d3f-743f-08df2f3b4cd2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|376014|82310400026|23010399003|36860700016|56012099006|5023799004|11063799006|261009223027099003|10067099003|22082099003|18002099003|6133799003; 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Each full cleanup/init cycle removes and recreates debugfs entries and, when eDMA is present, unregisters and reprobes the DMA controller. eDMA detection also allocates managed DMA linked-list memory that is retained until device detach. The inbound/outbound allocation bitmaps, outbound-address array and per-function descriptors already have allocation guards and can be reused. Track successful resource initialization in dw_pcie_ep_init_registers(). On later calls, restore the platform-specific registers, BAR defaults, PTM and non-sticky registers without repeating resource setup. Keep the register restoration helper private and use the existing public API for both initial setup and reset recovery. Clear the initialization flag on full cleanup so a later call performs resource setup again. Invalidate the outbound window bitmap, address array and MSI iATU cache after hardware has reset the iATU. This resets software bookkeeping; it does not disable or unmap live hardware windows. Document that reset recovery requires the hardware reset and quiesced EPF activity. Signed-off-by: Manikanta Maddireddy --- Changes V1 -> V2: - Fold init/reinit selection into dw_pcie_ep_init_registers() instead of adding a separate init-or-reinit API. - Keep the register restoration helper private and remove its public declarations, export and disabled-config stub. - Rename the outbound helper to dw_pcie_ep_reset_outbound_state() and explain that it resets software bookkeeping after hardware reset. - Document reset-recovery prerequisites and clarify resource lifetimes. - Update the title and commit message to describe resource reuse. .../pci/controller/dwc/pcie-designware-ep.c | 149 +++++++++++++----- drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 108 insertions(+), 42 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 0262d85ed390..3c26c03b42f0 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -1155,6 +1155,32 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, } EXPORT_SYMBOL_GPL(dw_pcie_ep_raise_msix_irq); +static void dw_pcie_ep_clear_msi_iatu(struct dw_pcie_ep *ep) +{ + ep->msi_iatu_mapped = false; + ep->msi_iatu_mapped_offset = 0; + ep->msi_msg_addr = 0; + ep->msi_map_size = 0; +} + +/* + * Reset only the software bookkeeping for outbound windows after hardware + * has reset the iATU. This does not disable or unmap live hardware windows. + */ +static void dw_pcie_ep_reset_outbound_state(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + + if (ep->ob_window_map) + bitmap_zero(ep->ob_window_map, pci->num_ob_windows); + + if (ep->outbound_addr) + memset(ep->outbound_addr, 0, + pci->num_ob_windows * sizeof(*ep->outbound_addr)); + + dw_pcie_ep_clear_msi_iatu(ep); +} + /** * dw_pcie_ep_cleanup - Cleanup DWC EP resources after fundamental reset * @ep: DWC EP device @@ -1169,11 +1195,12 @@ void dw_pcie_ep_cleanup(struct dw_pcie_ep *ep) if (ep->msi_iatu_mapped) { dw_pcie_ep_unmap_addr(ep->epc, 0, 0, ep->msi_mem_phys); - ep->msi_iatu_mapped = false; + dw_pcie_ep_clear_msi_iatu(ep); } dwc_pcie_debugfs_deinit(pci); dw_pcie_edma_remove(pci); + ep->resources_initialized = false; } EXPORT_SYMBOL_GPL(dw_pcie_ep_cleanup); @@ -1307,13 +1334,84 @@ static void dw_pcie_ep_disable_bars(struct dw_pcie_ep *ep) } } +static void dw_pcie_ep_init_ptm(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + u32 ptm_cap_base, reg; + + /* + * PCIe r6.0, section 7.9.15 states that for endpoints that support + * PTM, this capability structure is required in exactly one + * function, which controls the PTM behavior of all PTM capable + * functions. This indicates the PTM capability structure + * represents controller-level registers rather than per-function + * registers. + * + * Therefore, PTM capability registers are configured using the + * standard DBI accessors, instead of func_no indexed per-function + * accessors. + */ + ptm_cap_base = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM); + + /* + * PTM responder capability can be disabled only after disabling + * PTM root capability. + */ + if (ptm_cap_base) { + dw_pcie_dbi_ro_wr_en(pci); + reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP); + reg &= ~PCI_PTM_CAP_ROOT; + dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg); + + reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP); + reg &= ~(PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK); + dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg); + dw_pcie_dbi_ro_wr_dis(pci); + } +} + +/** + * dw_pcie_ep_reinit_registers - Reinitialize DWC EP reset-lost registers + * @ep: DWC EP device + * + * Restore the EP registers lost after a fundamental reset without repeating + * software resource setup. Hardware must already have reset the iATU; this + * helper invalidates software iATU state but does not disable live windows. + */ +static int dw_pcie_ep_reinit_registers(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + int ret; + + dw_pcie_ep_reset_outbound_state(ep); + + if (ep->ops->init) { + ret = ep->ops->init(ep); + if (ret) + return ret; + } + + dw_pcie_ep_disable_bars(ep); + dw_pcie_ep_init_ptm(ep); + dw_pcie_ep_init_non_sticky_registers(pci); + + return 0; +} + /** * dw_pcie_ep_init_registers - Initialize DWC EP specific registers * @ep: DWC EP device * * Initialize the registers (CSRs) specific to DWC EP. This API should be called * only when the endpoint receives an active refclk (either from host or - * generated locally). + * generated locally). The caller must quiesce EPF activity and ensure that + * hardware has reset the outbound iATU before calling this API after a + * fundamental reset. Cached outbound mappings are invalidated without + * disabling live hardware windows. + * + * The first successful call sets up the DWC EP software resources. Later + * calls restore reset-lost registers while retaining those resources until + * dw_pcie_ep_cleanup() or dw_pcie_ep_deinit(). */ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) { @@ -1321,7 +1419,6 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) struct dw_pcie_ep_func *ep_func; struct device *dev = pci->dev; struct pci_epc *epc = ep->epc; - u32 ptm_cap_base, reg; u8 hdr_type; u8 func_no; void *addr; @@ -1336,6 +1433,9 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) return -EIO; } + if (ep->resources_initialized) + return dw_pcie_ep_reinit_registers(ep); + dw_pcie_version_detect(pci); dw_pcie_iatu_detect(pci); @@ -1386,47 +1486,12 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep) list_add_tail(&ep_func->list, &ep->func_list); } - if (ep->ops->init) { - ret = ep->ops->init(ep); - if (ret) - goto err_remove_edma; - } - - dw_pcie_ep_disable_bars(ep); - - /* - * PCIe r6.0, section 7.9.15 states that for endpoints that support - * PTM, this capability structure is required in exactly one - * function, which controls the PTM behavior of all PTM capable - * functions. This indicates the PTM capability structure - * represents controller-level registers rather than per-function - * registers. - * - * Therefore, PTM capability registers are configured using the - * standard DBI accessors, instead of func_no indexed per-function - * accessors. - */ - ptm_cap_base = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PTM); - - /* - * PTM responder capability can be disabled only after disabling - * PTM root capability. - */ - if (ptm_cap_base) { - dw_pcie_dbi_ro_wr_en(pci); - reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP); - reg &= ~PCI_PTM_CAP_ROOT; - dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg); - - reg = dw_pcie_readl_dbi(pci, ptm_cap_base + PCI_PTM_CAP); - reg &= ~(PCI_PTM_CAP_RES | PCI_PTM_GRANULARITY_MASK); - dw_pcie_writel_dbi(pci, ptm_cap_base + PCI_PTM_CAP, reg); - dw_pcie_dbi_ro_wr_dis(pci); - } - - dw_pcie_ep_init_non_sticky_registers(pci); + ret = dw_pcie_ep_reinit_registers(ep); + if (ret) + goto err_remove_edma; dwc_pcie_debugfs_init(pci, DW_PCIE_EP_TYPE); + ep->resources_initialized = true; return 0; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index e7cdf1c69744..2d3563c3c4bf 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -513,6 +513,7 @@ struct dw_pcie_ep { unsigned long *ob_window_map; void __iomem *msi_mem; phys_addr_t msi_mem_phys; + bool resources_initialized; /* MSI outbound iATU state */ bool msi_iatu_mapped; -- 2.34.1