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Wed, 21 Oct 2026 04:41:55 -0700 (PDT) Received: from localhost.localdomain ([177.155.254.119]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-7cc91f9c7f1sm2365006137.0.2026.10.21.04.41.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 04:41:55 -0700 (PDT) From: Matheus Tagliari To: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= Cc: Matheus Tagliari , David Airlie , Simona Vetter , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] drm/radeon: process the VCE interrupt on SI and Trinity Date: Wed, 21 Oct 2026 08:41:17 -0300 Message-ID: <20261021114122.94008-2-mptagliari@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261021114122.94008-1-mptagliari@gmail.com> References: <20261021114122.94008-1-mptagliari@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit radeon_vce_fence_emit() ends every VCE fence with VCE_CMD_TRAP, which raises the VCE trap interrupt (IH src_id 167). cik_irq_process() handles it by calling radeon_fence_process() for the matching VCE ring, but si_irq_process() and evergreen_irq_process(), which serve the other ASICs with VCE1 (SI and Trinity/Richland), have no case for it. Add the same handling. The trap interrupt is not enabled on these ASICs yet, so this does not change behaviour on its own; the next patch enables it. The SI part was tested together with the next patch. The Trinity part mirrors the CIK and SI code and has not been tested on Trinity/Richland hardware. Fixes: a918efab631a ("drm/radeon: add VCE 1.0 support v4") Cc: stable@vger.kernel.org Signed-off-by: Matheus Tagliari --- drivers/gpu/drm/radeon/evergreen.c | 14 ++++++++++++++ drivers/gpu/drm/radeon/si.c | 14 ++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 3cbc6eedb..eb94916c8 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -4847,6 +4847,20 @@ int evergreen_irq_process(struct radeon_device *rdev) drm_dbg(ddev, "IH: UVD int: 0x%08x\n", src_data); radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); break; + case 167: /* VCE */ + drm_dbg(ddev, "IH: VCE int: 0x%08x\n", src_data); + switch (src_data) { + case 0: + radeon_fence_process(rdev, TN_RING_TYPE_VCE1_INDEX); + break; + case 1: + radeon_fence_process(rdev, TN_RING_TYPE_VCE2_INDEX); + break; + default: + drm_err(ddev, "Unhandled interrupt: %d %d\n", src_id, src_data); + break; + } + break; case 146: case 147: addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 4681ff286..af3c4026d 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -6347,6 +6347,20 @@ int si_irq_process(struct radeon_device *rdev) DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); break; + case 167: /* VCE */ + DRM_DEBUG("IH: VCE int: 0x%08x\n", src_data); + switch (src_data) { + case 0: + radeon_fence_process(rdev, TN_RING_TYPE_VCE1_INDEX); + break; + case 1: + radeon_fence_process(rdev, TN_RING_TYPE_VCE2_INDEX); + break; + default: + DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); + break; + } + break; case 146: case 147: addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); -- 2.47.3