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Wed, 21 Oct 2026 04:41:58 -0700 (PDT) Received: from localhost.localdomain ([177.155.254.119]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-7cc91f9c7f1sm2365006137.0.2026.10.21.04.41.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 04:41:58 -0700 (PDT) From: Matheus Tagliari To: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= Cc: Matheus Tagliari , David Airlie , Simona Vetter , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] drm/radeon/vce1: enable the VCE trap interrupt Date: Wed, 21 Oct 2026 08:41:18 -0300 Message-ID: <20261021114122.94008-3-mptagliari@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261021114122.94008-1-mptagliari@gmail.com> References: <20261021114122.94008-1-mptagliari@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit vce_v2_0 sets VCE_SYS_INT_TRAP_INTERRUPT_EN in VCE_SYS_INT_EN so that the VCE_CMD_TRAP emitted after each fence raises an interrupt. The VCE1 code, used by SI and Trinity/Richland, never does, and amdgpu's vce_v1_0 does (mmVCE_SYS_INT_EN, 0x8340, i.e. byte offset 0x20d00 on SI). VCE fences are therefore never processed from the interrupt handler and are only noticed when a fence wait times out. Enable the trap interrupt at the end of vce_v1_0_start(). Observed on a Radeon HD 8870M (Cape Verde, 1002:6821) with VCE firmware 50.0.1, Mesa 25.0.7 radeonsi and ffmpeg h264_vaapi on Debian 6.12.113: - Stock driver: the encode hangs after a few dozen frames ("ring 0 stalled", "ring 3 stalled", "GPU lockup"), and the reset does not recover ("failed VCE resume (-22)", "ring 0 test failed"). - With the hardware ring semaphores of the VCE ring disabled as a workaround, the hang is gone but encoding runs at 3.9 fps (~256 ms per frame), consistent with fences being noticed only by timeouts. - With this series: 640x360 for 1800 frames, 1280x720 for 900 frames and 1920x1080 for 600 frames, all in real time with no decode errors, and 191 fps at 720p / 91 fps at 1080p unthrottled. Four runtime suspend/resume cycles with an encode in between also worked. No lockup, reset, WARNING or error in the kernel log, with DPM and runtime PM enabled. Trinity/Richland shares this code and is covered by the previous patch, but I have no such hardware to test. Fixes: a918efab631a ("drm/radeon: add VCE 1.0 support v4") Cc: stable@vger.kernel.org Signed-off-by: Matheus Tagliari --- drivers/gpu/drm/radeon/sid.h | 2 ++ drivers/gpu/drm/radeon/vce_v1_0.c | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h index f9267b026..ba322de84 100644 --- a/drivers/gpu/drm/radeon/sid.h +++ b/drivers/gpu/drm/radeon/sid.h @@ -1878,6 +1878,8 @@ #define DMA_PACKET_NOP 0xf #define VCE_STATUS 0x20004 +#define VCE_SYS_INT_EN 0x20d00 +#define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3) #define VCE_VCPU_CNTL 0x20014 #define VCE_CLK_EN (1 << 0) #define VCE_VCPU_CACHE_OFFSET0 0x20024 diff --git a/drivers/gpu/drm/radeon/vce_v1_0.c b/drivers/gpu/drm/radeon/vce_v1_0.c index bdfbcf14b..0866e7fb0 100644 --- a/drivers/gpu/drm/radeon/vce_v1_0.c +++ b/drivers/gpu/drm/radeon/vce_v1_0.c @@ -350,6 +350,10 @@ int vce_v1_0_start(struct radeon_device *rdev) return r; } + /* enable the trap interrupt so that VCE fences are processed */ + WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, + ~VCE_SYS_INT_TRAP_INTERRUPT_EN); + return 0; } -- 2.47.3