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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ada49366fdsm928525a91.14.2026.10.21.13.53.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 13:53:19 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 13/14] drm/msm/a8xx: Switch to generated protect regs Date: Wed, 21 Oct 2026 13:41:38 -0700 Message-ID: <20261021204244.67160-14-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261021204244.67160-1-robin.clark@oss.qualcomm.com> References: <20261021204244.67160-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: ujuyhXA955j2bJeaNE7W5_AICFNe_EnW X-Proofpoint-ORIG-GUID: ujuyhXA955j2bJeaNE7W5_AICFNe_EnW X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA4MyBTYWx0ZWRfX+PoViyRHN/Rc qUqf6ITGH2FZSVbXNZ5WdrI4mYKl8CfwORW2S2XUmyNOatNlJ5MWbpkKNzoQYJjZh4Pu33B2duy /dYEf/WqAuB56U2u4t/+43c+mRxzQz8= X-Authority-Analysis: v=2.4 cv=KOzPn1Fo c=1 sm=1 tr=0 ts=6ad92641 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=JcQOObtfp6PrThPhMQoA:9 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA4MyBTYWx0ZWRfX+l3RD9lUbamD WgQ5md2inW7Y248RxciJBvavhOfxjhJwYJfLLOWCpq2OEDupkwzkjUnZQ5s5Wmayc1X6CDk6iiX mIM+AoQ3lynoRiQSmJfUqz4bvugjBSB01p3EXM615hZ+GiX2M2VMUK0eYitdiwZyqIgIgLaHpsd keDeGDpzRyJaF/JxbQL0+Ajz3yau5wLLHS6us1U76llJvfHW2yw/SUYOHKSA6zT3MU1jO0Er4HT IfJkngTqRqYej7tDxrSdbesEgi68WOeSbsH3xYKf+qptunBT+RCctl8tu6I6PTrcsBTfCkr6lkl cGLWEvZoaF2gOdvgL48ZcHtSHNzgPSZPQ1JCQehjC8+7pruE4c0msc9ZjDDU2gPb++koRPchi8k Xvw2SoYJyxWwUV/OBqSWGkbtJvcpsitzFaZ2hwnWJYCzGy+xbPcSgCEJwNPsthnZU0fRHi6FxfR LcQ0fj67WOLx+VzsYTg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 impostorscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210083 These also fix some perfcntr SEL regs which were mistakenly blocked since we previously just copied the protect tables from downstream kgsl (and only sometimes remembered to fix these). Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a8xx_catalog.c | 301 +--------------------- 1 file changed, 13 insertions(+), 288 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_catalog.c b/drivers/gpu/drm/msm/adreno/a8xx_catalog.c index 7a9080e7b11b..e0dcf5ec6b7b 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_catalog.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_catalog.c @@ -18,58 +18,6 @@ #include "catalog/adreno_milos.h" #include "catalog/adreno_pakala.h" -static const u32 a830_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00000, 0x03a3), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x0026), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae02, 0x0004), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x036f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0787), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x20000, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0381), - A6XX_PROTECT_NORDWR(0x27882, 0x0001), - A6XX_PROTECT_NORDWR(0x27c02, 0x0000), -}; -DECLARE_ADRENO_PROTECT(a830_protect, 64); - static const u32 a830_pwrup_reglist_regs[] = { REG_A6XX_UCHE_MODE_CNTL, REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, @@ -241,63 +189,6 @@ static const struct adreno_reglist_pipe a830_dyn_pwrup_reglist_regs[] = { }; DECLARE_ADRENO_REGLIST_PIPE_LIST(a830_dyn_pwrup_reglist); -static const u32 x285_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00008, 0x039b), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x0026), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x0082c, 0x0000), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), - A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), - A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), - A6XX_PROTECT_NORDWR(0x0af00, 0x027f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0507), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0385), - A6XX_PROTECT_NORDWR(0x27882, 0x000a), - A6XX_PROTECT_NORDWR(0x27c06, 0x0000), -}; - -DECLARE_ADRENO_PROTECT(x285_protect, 15); - static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = { { REG_A8XX_GRAS_TSEFE_DBG_ECO_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, { REG_A8XX_GRAS_NC_MODE_CNTL, 0, BIT(PIPE_BV) | BIT(PIPE_BR) }, @@ -336,57 +227,6 @@ static const struct adreno_reglist_pipe x285_dyn_pwrup_reglist_regs[] = { }; DECLARE_ADRENO_REGLIST_PIPE_LIST(x285_dyn_pwrup_reglist); -static const u32 a810_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00000, 0x03a3), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x0026), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x036f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0787), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x20000, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0381), - A6XX_PROTECT_NORDWR(0x27882, 0x0001), - A6XX_PROTECT_NORDWR(0x27c02, 0x0000), -}; -DECLARE_ADRENO_PROTECT(a810_protect, 64); - static const uint32_t a810_pwrup_reglist_regs[] = { REG_A6XX_UCHE_MODE_CNTL, REG_A8XX_UCHE_VARB_IDLE_TIMEOUT, @@ -626,64 +466,6 @@ struct a6xx_hfi_limits_tbl x285_limits_tbl[] = { }; DECLARE_ADRENO_LIMITS_TABLE(x285_limits); -static const u32 a840_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00008, 0x039b), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x001b), - A6XX_PROTECT_NORDWR(0x00775, 0x000a), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_NORDWR(0x00c07, 0x0008), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), - A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae02, 0x0004), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), - A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), - A6XX_PROTECT_NORDWR(0x0af00, 0x027f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1b400, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0507), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0385), - A6XX_PROTECT_NORDWR(0x27882, 0x0009), - A6XX_PROTECT_NORDWR(0x27c06, 0x0000), -}; -DECLARE_ADRENO_PROTECT(a840_protect, 15); - static const struct adreno_reglist a840_gbif[] = { { REG_A6XX_GBIF_QSB_SIDE0, 0x00071e20 }, { REG_A6XX_GBIF_QSB_SIDE1, 0x00071e20 }, @@ -956,67 +738,6 @@ struct a6xx_hfi_limits_tbl a840_limits_tbl[] = { }; DECLARE_ADRENO_LIMITS_TABLE(a840_limits); -static const u32 a850_protect_regs[] = { - A6XX_PROTECT_RDONLY(0x00008, 0x039b), - A6XX_PROTECT_RDONLY(0x003b4, 0x008b), - A6XX_PROTECT_NORDWR(0x00440, 0x001f), - A6XX_PROTECT_RDONLY(0x00580, 0x005f), - A6XX_PROTECT_NORDWR(0x005e0, 0x011f), - A6XX_PROTECT_RDONLY(0x0074a, 0x0005), - A6XX_PROTECT_RDONLY(0x00759, 0x001b), - A6XX_PROTECT_NORDWR(0x00775, 0x000a), - A6XX_PROTECT_RDONLY(0x00789, 0x0000), - A6XX_PROTECT_RDONLY(0x0078c, 0x0013), - A6XX_PROTECT_NORDWR(0x00800, 0x0029), - A6XX_PROTECT_NORDWR(0x00837, 0x00af), - A6XX_PROTECT_RDONLY(0x008e7, 0x00c9), - A6XX_PROTECT_NORDWR(0x008ec, 0x00c3), - A6XX_PROTECT_NORDWR(0x009b1, 0x0250), - A6XX_PROTECT_NORDWR(0x00c07, 0x0008), - A6XX_PROTECT_RDONLY(0x00ce0, 0x0001), - A6XX_PROTECT_RDONLY(0x00df0, 0x0000), - A6XX_PROTECT_NORDWR(0x00df1, 0x0000), - A6XX_PROTECT_NORDWR(0x00df5, 0x0003), - A6XX_PROTECT_RDONLY(0x00df9, 0x0007), - A6XX_PROTECT_NORDWR(0x00e01, 0x0000), - A6XX_PROTECT_NORDWR(0x00e03, 0x1fff), - A6XX_PROTECT_NORDWR(0x03c00, 0x00c5), - A6XX_PROTECT_RDONLY(0x03cc6, 0x0039), - A6XX_PROTECT_NORDWR(0x03d00, 0x1fff), - A6XX_PROTECT_NORDWR(0x08600, 0x01ff), - A6XX_PROTECT_NORDWR(0x08e00, 0x00ff), - A6XX_PROTECT_RDONLY(0x08f00, 0x0000), - A6XX_PROTECT_NORDWR(0x08f01, 0x01be), - A6XX_PROTECT_NORDWR(0x09600, 0x01ff), - A6XX_PROTECT_RDONLY(0x0981a, 0x02e5), - A6XX_PROTECT_NORDWR(0x09e00, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a600, 0x01ff), - A6XX_PROTECT_NORDWR(0x0a82e, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae00, 0x0000), - A6XX_PROTECT_NORDWR(0x0ae02, 0x0004), - A6XX_PROTECT_NORDWR(0x0ae08, 0x0006), - A6XX_PROTECT_NORDWR(0x0ae10, 0x00bf), - A6XX_PROTECT_RDONLY(0x0aed0, 0x002f), - A6XX_PROTECT_NORDWR(0x0af00, 0x027f), - A6XX_PROTECT_NORDWR(0x0b600, 0x1fff), - A6XX_PROTECT_NORDWR(0x0dc00, 0x1fff), - A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x18400, 0x003f), - A6XX_PROTECT_RDONLY(0x18440, 0x013f), - A6XX_PROTECT_NORDWR(0x18580, 0x1fff), - A6XX_PROTECT_NORDWR(0x1ac00, 0x1fff), - A6XX_PROTECT_NORDWR(0x1cc00, 0x1fff), - A6XX_PROTECT_NORDWR(0x1f400, 0x0477), - A6XX_PROTECT_RDONLY(0x1f878, 0x0507), - A6XX_PROTECT_NORDWR(0x1f930, 0x0329), - A6XX_PROTECT_NORDWR(0x1fd80, 0x1fff), - A6XX_PROTECT_NORDWR(0x27800, 0x007f), - A6XX_PROTECT_RDONLY(0x27880, 0x0385), - A6XX_PROTECT_NORDWR(0x27882, 0x0035), - A6XX_PROTECT_NORDWR(0x27c06, 0x0000), -}; -DECLARE_ADRENO_PROTECT(a850_protect, 15); - static const u32 a850_pwrup_reglist_regs[] = { REG_A8XX_RB_CMP_NC_MODE_CNTL, REG_A8XX_SP_HLSQ_GC_GMEM_RANGE_MIN, @@ -1222,7 +943,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_IFPC, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &a830_protect, + .protect = &pakala_protect, .nonctxt_reglist = pakala_nonctxt_regs, .pwrup_reglist = &a830_pwrup_reglist, .dyn_pwrup_reglist = &a830_dyn_pwrup_reglist, @@ -1267,7 +988,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_SOFTFUSE, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &x285_protect, + .protect = &glymur_protect, .nonctxt_reglist = glymur_nonctxt_regs, .pwrup_reglist = &a840_pwrup_reglist, .dyn_pwrup_reglist = &x285_dyn_pwrup_reglist, @@ -1312,7 +1033,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_IFPC, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &a840_protect, + .protect = &kaanapali_protect, .nonctxt_reglist = kaanapali_nonctxt_regs, .pwrup_reglist = &a840_pwrup_reglist, .dyn_pwrup_reglist = &a840_dyn_pwrup_reglist, @@ -1358,7 +1079,7 @@ static const struct adreno_info a8xx_gpus[] = { .funcs = &a8xx_gpu_funcs, .zapfw = "gen80300_zap.mbn", .a6xx = &(const struct a6xx_info) { - .protect = &a810_protect, + .protect = &milos_protect, .nonctxt_reglist = milos_nonctxt_regs, .pwrup_reglist = &a810_pwrup_reglist, .dyn_pwrup_reglist = &a810_dyn_pwrup_reglist, @@ -1401,7 +1122,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_SOFTFUSE, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &x285_protect, + .protect = &glymur_protect, .nonctxt_reglist = glymur_nonctxt_regs, .pwrup_reglist = &a840_pwrup_reglist, .dyn_pwrup_reglist = &x285_dyn_pwrup_reglist, @@ -1444,7 +1165,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_IFPC, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &a850_protect, + .protect = &maili_protect, .nonctxt_reglist = maili_nonctxt_regs, .pwrup_reglist = &a850_pwrup_reglist, .dyn_pwrup_reglist = &a850_dyn_pwrup_reglist, @@ -1488,7 +1209,7 @@ static const struct adreno_info a8xx_gpus[] = { ADRENO_QUIRK_IFPC, .funcs = &a8xx_gpu_funcs, .a6xx = &(const struct a6xx_info) { - .protect = &a850_protect, + .protect = &hawi_protect, .nonctxt_reglist = hawi_nonctxt_regs, .pwrup_reglist = &a850_pwrup_reglist, .dyn_pwrup_reglist = &a850_dyn_pwrup_reglist, @@ -1523,6 +1244,10 @@ DECLARE_ADRENO_GPULIST(a8xx); static inline __always_unused void __build_asserts(void) { - BUILD_BUG_ON(a810_protect.count > a810_protect.count_max); - BUILD_BUG_ON(a830_protect.count > a830_protect.count_max); + BUILD_BUG_ON(glymur_protect.count > glymur_protect.count_max); + BUILD_BUG_ON(hawi_protect.count > hawi_protect.count_max); + BUILD_BUG_ON(kaanapali_protect.count > kaanapali_protect.count_max); + BUILD_BUG_ON(maili_protect.count > maili_protect.count_max); + BUILD_BUG_ON(milos_protect.count > milos_protect.count_max); + BUILD_BUG_ON(pakala_protect.count > pakala_protect.count_max); } -- 2.56.0