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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ada4896c71sm1025666a91.6.2026.10.21.13.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 13:52:39 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 03/14] drm/msm/a8xx: Add a8xx_aperture_acquire_raw() Date: Wed, 21 Oct 2026 13:41:28 -0700 Message-ID: <20261021204244.67160-4-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261021204244.67160-1-robin.clark@oss.qualcomm.com> References: <20261021204244.67160-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=HLhWhYtv c=1 sm=1 tr=0 ts=6ad92619 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=qGl0e74_xy6xiHm5yPkA:9 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-GUID: Nk04i-AZO5zCS72CTv02cmw16MLzYsvo X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA4MyBTYWx0ZWRfX0d6jvJOHzMOc hhz7jvHoF5/0Gm7SA38zAxi3CpGuRckLEN5n+B1nPaHPIfp8Q5LEurLusXepSXXa1YFsbKCv93n NrpWT+QNNzA5WVmtFD5ylxgPRT43VNk= X-Proofpoint-ORIG-GUID: Nk04i-AZO5zCS72CTv02cmw16MLzYsvo X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA4MyBTYWx0ZWRfX+x5y28W1W9YA HTKzOG7x6pqdW+GKrkVEFPcnx+hzixM0cyGL1Eayi6GM3cC5R9EVwRn9o2m0T4SgwoLS9503GOz X5N4c11g3lDsFYow45XAoByAwCTmXmDgW/iseLfPQ+nqpyasPrFIBezrUILUGzq2X5WNXB6QEqR fy4NQ0BwnKRVy0sCltaJwivAUosDbQ93FIXvI1SzkwAdmM5YMbQtb81+Diq3GUqc5PDnk/2sEOV QFjYUbFAjPFZVu0HdFXooZBclrWlBRm/LOun5BCnZjKPSb2XTuKl/s1iIihwm996FlDkQLAOAwx sw1/oQjMHckQA1q9MSN4wl1YG0A4QJ0iSbz1z/kaMwBoIjs2t+xofMcAcenNj4ORZRkTcukPYU3 B47eDPx/TFtkBPCQfZA4kXNxLNArVS+2sjTPd+xWn9YJZVIvu0KG9Lv8LAb4fSv2zpYV6i41pW4 tICfsnFWAzE7O5m3Y3A== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 spamscore=0 adultscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210083 The snapshot code will need more control, setting additional bitfields. Rather than add a list of additional args, add a helper to acquire the aperture which directly takes a reg value. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 21 +++++++++++++-------- 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index fb000b79fe2f..2a2ddba6761f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -348,6 +348,7 @@ void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); void a6xx_flush_yield(struct msm_gpu *gpu, struct msm_ringbuffer *ring); int a6xx_zap_shader_init(struct msm_gpu *gpu); +void a8xx_aperture_acquire_raw(struct msm_gpu *gpu, u32 val, unsigned long *flags); void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags); void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags); void a8xx_aperture_clear(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index a14379e26fbe..a0983e2ee641 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -16,13 +16,10 @@ #define GPU_PAS_ID 13 -static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 slice) +static void a8xx_aperture_slice_set(struct msm_gpu *gpu, u32 val) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); - u32 val; - - val = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe) | A8XX_CP_APERTURE_CNTL_HOST_SLICEID(slice); if (a6xx_gpu->cached_aperture == val) return; @@ -32,14 +29,20 @@ static void a8xx_aperture_slice_set(struct msm_gpu *gpu, enum adreno_pipe pipe, a6xx_gpu->cached_aperture = val; } -void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) +void a8xx_aperture_acquire_raw(struct msm_gpu *gpu, u32 val, unsigned long *flags) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); spin_lock_irqsave(&a6xx_gpu->aperture_lock, *flags); - a8xx_aperture_slice_set(gpu, pipe, 0); + a8xx_aperture_slice_set(gpu, val); + +} + +void a8xx_aperture_acquire(struct msm_gpu *gpu, enum adreno_pipe pipe, unsigned long *flags) +{ + a8xx_aperture_acquire_raw(gpu, A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe), flags); } void a8xx_aperture_release(struct msm_gpu *gpu, unsigned long flags) @@ -74,8 +77,10 @@ static u32 a8xx_read_pipe_slice(struct msm_gpu *gpu, enum adreno_pipe pipe, u32 unsigned long flags; u32 val; - spin_lock_irqsave(&a6xx_gpu->aperture_lock, flags); - a8xx_aperture_slice_set(gpu, pipe, slice); + a8xx_aperture_acquire_raw(gpu, + A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe) | + A8XX_CP_APERTURE_CNTL_HOST_SLICEID(slice), + &flags); val = gpu_read(gpu, offset); spin_unlock_irqrestore(&a6xx_gpu->aperture_lock, flags); -- 2.56.0