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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ada4933d16sm962668a91.13.2026.10.21.13.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 13:52:44 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Rob Clark , Konrad Dybcio , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 06/14] drm/msm/a8xx: Allow nonctx reglist to include GMU regs Date: Wed, 21 Oct 2026 13:41:31 -0700 Message-ID: <20261021204244.67160-7-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261021204244.67160-1-robin.clark@oss.qualcomm.com> References: <20261021204244.67160-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA4MyBTYWx0ZWRfX9aaStfkIYFg6 kIUdL24Tyrkhv33RYU5Pdn4f0DT1hvqt/25P8Z7ds/CrL/uXmx+L1CD0W4r1FxZTmQhZ3NLrFuM Gdrz7WcAD4sNucYsKKgoz6errICL978= X-Authority-Analysis: v=2.4 cv=eJaGH3p1 c=1 sm=1 tr=0 ts=6ad9261f cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=cg0wMmP-TNBUvudz7-YA:9 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: 5Hk0NHe-zAYyuzL_LfUb7OJDwU06v3yQ X-Proofpoint-ORIG-GUID: 5Hk0NHe-zAYyuzL_LfUb7OJDwU06v3yQ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA4MyBTYWx0ZWRfX6Z1ov/4gwCQe rhSFwI2x/tlPnWBQbXQ/MLoKAfee6sdrDh5WN52nwzbYTPAy7ErTAmGCcF0PbzECfcikQKqG1mH 28sZzO8fQ6DSws/ACEpDe++vAJ9zuSpbPh2wyhFAUwZlHGbJT3ruaxW7EZxJ8xlqx9VNsM/bJrM k+fbPS0jiNme4r7M/RgWLjUYJDKdB+Bws0ZohkaEq5a1+Uc8gOS0ts4rRx1DlJB4EjrE3wfKS1m eZT3Zd+U8EGa6M03dAVx/42PR0dgG047DiwMKm7i7ctmj4d4eU59isQ5zD6hQsWe6YAtcvzWeq+ lTMoJU1+7MYpFefI91RSNbaFNU5IDj3yEqzT/hpMXjLFJ4vXzO87BukSdLPrqwyr1mTbrV4gdsz ZdVOEfXj9/XnA29ZuNYMFgFF3EMVVXO2G5+73gX1kmYubPPqAw0YRBQZ8eB46Qo4uGaEsa202Ts PByc2oWYD0A/eBLeURQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 adultscore=0 spamscore=0 clxscore=1015 bulkscore=0 phishscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210083 >From hw PoV, it's all part of the GPU. But from dt perspective it is it's own device with a separate io space. So we need to detect this and direct writes to the correct place. Signed-off-by: Rob Clark Acked-by: Konrad Dybcio --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index 8e91edf16ec2..795c16d88f45 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -370,6 +370,7 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a6xx_gmu *gmu = &to_a6xx_gpu(adreno_gpu)->gmu; const struct a6xx_info *info = adreno_gpu->info->a6xx; const struct adreno_reglist_pipe *regs = info->nonctxt_reglist; unsigned int pipe_id, i; @@ -389,7 +390,11 @@ static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT) *gmem_protect = regs[i].value; - gpu_write(gpu, regs[i].offset, regs[i].value); + if ((regs[i].offset << 2) >= gmu->mmio_offset) { + gmu_write(gmu, regs[i].offset, regs[i].value); + } else { + gpu_write(gpu, regs[i].offset, regs[i].value); + } } a8xx_aperture_release(gpu, flags); -- 2.56.0