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[67.168.198.145]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3ad83466e46sm3157774a91.1.2026.10.21.13.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 13:52:46 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Alexander Koskovich , Jie Zhang , Akhil P Oommen , Bhaskar Reddy Valluru , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 07/14] drm/msm/a8xx: Stop getting GMEM_PROTECT from nonctx list Date: Wed, 21 Oct 2026 13:41:32 -0700 Message-ID: <20261021204244.67160-8-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261021204244.67160-1-robin.clark@oss.qualcomm.com> References: <20261021204244.67160-1-robin.clark@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDA4MyBTYWx0ZWRfXwFU2zVRrUldx RdwZzGRQlDT2s/YPcU1G1gH2w16TPfvlSPd9j9L9Eyb6uFxTTxhuQ5OcCz2uMXz9oE65OfsjEjI 5dzCl6a5r46zrhOCFWwy0XBQtZdDNqw= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDA4MyBTYWx0ZWRfX9M76yYJPrrH6 /iJTeEItbgZ3QE7kI7erZPAvbTY8h5UAOMTKs6oPuJIG8mbbx14YqNJd2NE9E/iPYSy4t56St1w P+ZSzZEjD+dV4/8Ul2APE73FoMUX16havvhAQeummaqsKE7+SkYknOpDlw7rkHnNk/CqAnZmsJV St9ktVtMn5VZ1bjhUWs+CsnKzb0p4AtEqwqLT70SyYPJ6+m/dvrSQqGl7n/d6yo/dSVSbTHnYXu MAjVL7Nfn4J2Q+59S9TSvJ9XlbcHiKvI7o45EiPk5hdc2Kfi5x1MQbSaKriTr0+WAsBXgya3uVA BhE0T7364a+dlsdZv2T6H3zgiDjcdBR03P5Yn1JubLj4VlETVK2XSrjFhAnUGCe5faENXrhNrjv c5ZljMiJbaBC+MeCUbbZ3NMumZk6GIahLYkFYElSTWm5gzx9dY4wC3rxitvUGrkZz2qoKhxqmZd HxSnuAQ7jT62gbFvAzw== X-Proofpoint-ORIG-GUID: WxGDUavUMe2Tvmkvkwa-2sXfjXNQQ1UY X-Proofpoint-GUID: WxGDUavUMe2Tvmkvkwa-2sXfjXNQQ1UY X-Authority-Analysis: v=2.4 cv=K/+3jCWI c=1 sm=1 tr=0 ts=6ad92621 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=6Rn/7xRx7Ub4NEhlm8k1cw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=b4MSL0WmfgirtTH71F4A:9 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-21_06,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 spamscore=0 bulkscore=0 suspectscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210083 We can just simplify things and calculate the value, instead of manually adding it to the nonctx list. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c index 795c16d88f45..a6146372cf7e 100644 --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c @@ -367,7 +367,7 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) hbb_lo << 1 | ubwc_mode); } -static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) +static void a8xx_nonctxt_config(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gmu *gmu = &to_a6xx_gpu(adreno_gpu)->gmu; @@ -387,9 +387,6 @@ static void a8xx_nonctxt_config(struct msm_gpu *gpu, u32 *gmem_protect) if (!(BIT(pipe_id) & regs[i].pipe)) continue; - if (regs[i].offset == REG_A8XX_RB_GC_GMEM_PROTECT) - *gmem_protect = regs[i].value; - if ((regs[i].offset << 2) >= gmu->mmio_offset) { gmu_write(gmu, regs[i].offset, regs[i].value); } else { @@ -635,7 +632,6 @@ static int hw_init(struct msm_gpu *gpu) struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu = &a6xx_gpu->gmu; unsigned int pipe_id, i; - u32 gmem_protect = 0; u64 gmem_range_min; int ret; @@ -716,7 +712,7 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A8XX_UCHE_CLIENT_PF, BIT(7) | 0x1); - a8xx_nonctxt_config(gpu, &gmem_protect); + a8xx_nonctxt_config(gpu); /* Enable fault detection */ gpu_write(gpu, REG_A8XX_RBBM_INTERFACE_HANG_INT_CNTL, BIT(30) | 0xcfffff); @@ -835,8 +831,8 @@ static int hw_init(struct msm_gpu *gpu) * GMEM_PROTECT register should be programmed after GPU is transitioned to * non-secure mode */ - a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_GC_GMEM_PROTECT, gmem_protect); - WARN_ON(!gmem_protect); + a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_RB_GC_GMEM_PROTECT, + (adreno_gpu->info->gmem / SZ_4K) << 16); a8xx_aperture_clear(gpu); if (!a6xx_gpu->pwrup_reglist_emitted) { -- 2.56.0