[PATCH 0/2] arm64: dts: freescale: Re-enable A72 cluster on i.MX8QM boards

["Peng Fan (OSS)" <peng.fan@oss.nxp.com>]

The ERR050104 cache coherency workaround for the NXP i.MX8QuadMax and
i.MX8QuadPlus SoCs has been merged upstream as commit d44e08dab27d
("arm64: errata: Add NXP i.MX8QM/8QP workaround for A53 cache coherency
issue").

The workaround addresses a hardware defect where the upper address bits
of the ARADDR and ACADDR buses within the Cortex-A53 subsystem were
incorrectly connected, causing TLBI and IC maintenance operations
exchanged between the A53 and A72 clusters to be corrupted.

Before the software workaround was available, affected board DTS files
worked around this issue at the DT level by removing the Cortex-A72 CPU
nodes (cpu@100, cpu@101), the cpu-map topology, and associated thermal
zones, effectively running the SoC as a single A53-only cluster.

With the kernel-side fix in place, these DT-level workarounds could be
dropped.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Peng Fan (2):
      arm64: dts: imx8qm-mek: Re-enable A72 cluster after ERR050104 workaround
      arm64: dts: imx8qm-tqma8qm: Re-enable A72 cluster after ERR050104 workaround

 arch/arm64/boot/dts/freescale/imx8qm-mek.dts      | 10 ----------
 arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi |  7 -------
 2 files changed, 17 deletions(-)
---
base-commit: 4403278e4ea2f654f8130a5c03eb8b4516a0f201
change-id: 20261022-8qm-875d0b4b3e7d

Best regards,
--  
Peng Fan <peng.fan@nxp.com>