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charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261022-a210-init-v1-2-5e438f972d24@iscas.ac.cn> References: <20261022-a210-init-v1-0-5e438f972d24@iscas.ac.cn> In-Reply-To: <20261022-a210-init-v1-0-5e438f972d24@iscas.ac.cn> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Zhiguo Zhu , Stephen Boyd , Brian Masney , Jerome Brunet , Philipp Zabel , Linus Walleij , Bartosz Golaszewski , Thomas Gleixner , Radu Rendec , Samuel Holland , Daniel Lezcano , Anup Patel , Icenowy Zheng , Drew Fustini Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Paul Walmsley , Han Gao X-Mailer: b4 0.16.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792612403; l=1013; i=gaohan@iscas.ac.cn; s=20261021; h=from:subject:message-id; bh=4BCg+toIRbmSQPVtgy4Q0XzWNjGrXKkDc5R8if2Rdc4=; b=ABWPT2/vC2QfeXMG1/w9VVAjTJqqfTPVM/54tCmkLQLDLnCqT6XiKVKu6QeSqctxfeROaimly ON8hQqfPoLCCyeZZG8KvXFMFwq3DHpbth19Te47OI7Ps3hU4AD7JxzN X-Developer-Key: i=gaohan@iscas.ac.cn; a=ed25519; pk=J8WHEK3filS86QaCaIHDGafqhxKyQ4K7+vFgRirTIiY= X-Endpoint-Received: by B4 Relay for gaohan@iscas.ac.cn/20261021 with auth_id=1262 X-Original-From: Han Gao Reply-To: gaohan@iscas.ac.cn From: Zhiguo Zhu Add the ARCH_ZHIHE option for the Zhihe A210 SoC. Signed-off-by: Zhiguo Zhu Co-developed-by: Han Gao Signed-off-by: Han Gao --- arch/riscv/Kconfig.socs | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index cecbce0c4983..b9863ebd88c7 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -91,6 +91,16 @@ config ARCH_ULTRARISC This enables support for UltraRISC SoC platform hardware, including boards based on the UR-DP1000. +config ARCH_ZHIHE + bool "ZhiHe SoCs" + depends on 64BIT && MMU + select ARCH_HAS_RESET_CONTROLLER + help + Enable support for the Zhihe A210 SoC. + A210 has four C908 and four C920 RISC-V CPU cores. + Supported boards include the Melon Pi V1 and V2. + Say Y here to build a kernel for these boards. + config ARCH_VIRT bool "QEMU Virt Machine" select POWER_RESET -- 2.55.0