From: Conor Dooley <conor@kernel.org>
To: rodrigo.alencar@analog.com
Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org,
linux@analog.com, devicetree@vger.kernel.org,
linux-pwm@vger.kernel.org, linux-doc@vger.kernel.org,
"Jonathan Cameron" <jonathan.cameron@oss.qualcomm.com>,
"Olivier Moysan" <olivier.moysan@foss.st.com>,
"Jonathan Cameron" <jic23@kernel.org>,
"David Lechner" <dlechner@baylibre.com>,
"Andy Shevchenko" <andy@kernel.org>,
"Michael Hennerich" <Michael.Hennerich@analog.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Uwe Kleine-König" <ukleinek@kernel.org>,
"Jonathan Corbet" <corbet@lwn.net>,
"Shuah Khan" <skhan@linuxfoundation.org>,
"Randy Dunlap" <rdunlap@infradead.org>
Subject: Re: [PATCH v2 03/10] dt-bindings: iio: frequency: add adi,ad9910-axi-backend
Date: Thu, 22 Oct 2026 19:38:52 +0100 [thread overview]
Message-ID: <20261022-banish-scenic-030717ca503e@spud> (raw)
In-Reply-To: <20261022-ad9910-backend-support-v2-3-0ff7f0bff326@analog.com>
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On Thu, Oct 22, 2026 at 12:19:01PM -0300, Rodrigo Alencar via B4 Relay wrote:
> From: Rodrigo Alencar <rodrigo.alencar@analog.com>
>
> Add bindings for the AD9910 AXI backend IP core. The FPGA IP core
> interfaces with the data and control pins of the AD9910 DDS, streaming
> data from memory via DMA into the 18-bit parallel data port (F[1:0] and
> D[15:0] pins), which is clocked by the PDCLK output of the device. It
> also drives the PROFILE[2:0] pins and the DRCTL pin, which controls the
> slope direction of the digital ramp generator (DRG). The DRCTL pin is
> driven by a PWM generator, so the IP core is described both as an IIO
> backend and as a PWM provider.
>
> Signed-off-by: Rodrigo Alencar <rodrigo.alencar@analog.com>
> ---
> .../iio/frequency/adi,ad9910-axi-backend.yaml | 74 ++++++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 75 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,ad9910-axi-backend.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,ad9910-axi-backend.yaml
> new file mode 100644
> index 000000000000..20c45fbaf945
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/frequency/adi,ad9910-axi-backend.yaml
> @@ -0,0 +1,74 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/frequency/adi,ad9910-axi-backend.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog Devices AD9910 AXI Backend IP core
> +
> +maintainers:
> + - Rodrigo Alencar <rodrigo.alencar@analog.com>
> +
> +description:
> + FPGA IP core that interfaces with the data and control pins of the AD9910
> + Direct Digital Synthesizer. The SPI bus is used as the control interface
> + of the AD9910 device, while this IP core streams data from memory via DMA
> + into the 18-bit parallel data port (F[1:0] and D[15:0] pins), which is
> + clocked by the PDCLK output of the AD9910. The IP core also drives the
> + PROFILE[2:0] pins for profile selection and provides a PWM generator that
> + drives the DRCTL pin, controlling the digital ramp generator (DRG) slope
> + direction.
> +
> + https://developer.analog.com/docs/hdl/latest/library/axi_ad9910/index.html
> +
> +properties:
> + compatible:
> + const: adi,ad9910-axi-backend
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> + description: AXI bus clock (s_axi_aclk).
> +
> + dmas:
> + maxItems: 1
> +
> + dma-names:
> + items:
> + - const: tx
> +
> + '#io-backend-cells':
> + const: 0
> +
> + '#pwm-cells':
> + const: 3
> + description:
> + The first cell must be 0, as only the DRCTL PWM output is available.
I was about to ack this, but the wording here caught my eye. Are there
other PWMs that are unavailable?
> + The second cell is the PWM period in nanoseconds and the third cell
> + holds the PWM flags.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - dmas
> + - dma-names
> + - '#io-backend-cells'
> + - '#pwm-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + ad9910_backend: dds-backend@44a00000 {
> + compatible = "adi,ad9910-axi-backend";
> + reg = <0x44a00000 0x10000>;
> + clocks = <&clkc 15>;
> + dmas = <&tx_dma 0>;
> + dma-names = "tx";
> + #io-backend-cells = <0>;
> + #pwm-cells = <3>;
> + };
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 52024397dc78..351ec0bca477 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1731,6 +1731,7 @@ S: Supported
> W: https://ez.analog.com/linux-software-drivers
> F: Documentation/ABI/testing/debugfs-iio-ad9910
> F: Documentation/ABI/testing/sysfs-bus-iio-frequency-ad9910
> +F: Documentation/devicetree/bindings/iio/frequency/adi,ad9910-axi-backend.yaml
> F: Documentation/devicetree/bindings/iio/frequency/adi,ad9910.yaml
> F: Documentation/iio/ad9910.rst
> F: drivers/iio/frequency/ad9910.c
>
> --
> 2.43.0
>
>
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next prev parent reply other threads:[~2026-10-22 18:38 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-22 15:18 [PATCH v2 00/10] iio: frequency: ad9910: add IIO backend support Rodrigo Alencar via B4 Relay
2026-10-22 15:18 ` [PATCH v2 01/10] iio: frequency: ad9910: powerdown fix Rodrigo Alencar via B4 Relay
2026-10-22 15:19 ` [PATCH v2 02/10] iio: backend: add devm_iio_backend_get_optional() Rodrigo Alencar via B4 Relay
2026-10-22 15:19 ` [PATCH v2 03/10] dt-bindings: iio: frequency: add adi,ad9910-axi-backend Rodrigo Alencar via B4 Relay
2026-10-22 18:38 ` Conor Dooley [this message]
2026-10-23 11:15 ` Rodrigo Alencar
2026-10-23 17:39 ` Conor Dooley
2026-10-22 15:19 ` [PATCH v2 04/10] dt-bindings: iio: frequency: ad9910: add io-backends property Rodrigo Alencar via B4 Relay
2026-10-22 15:19 ` [PATCH v2 05/10] iio: frequency: ad9910: move channel indexes into a shared header Rodrigo Alencar via B4 Relay
2026-10-22 15:19 ` [PATCH v2 06/10] iio: frequency: ad9910: add axi backend driver Rodrigo Alencar via B4 Relay
2026-10-22 15:19 ` [PATCH v2 07/10] iio: frequency: ad9910: support drctl control Rodrigo Alencar via B4 Relay
2026-10-23 10:40 ` Rodrigo Alencar
2026-10-23 14:48 ` Nuno Sá
2026-10-22 15:19 ` [PATCH v2 08/10] iio: frequency: ad9910: support iio backend Rodrigo Alencar via B4 Relay
2026-10-22 15:19 ` [PATCH v2 09/10] iio: ABI: add integration_time for output channels Rodrigo Alencar via B4 Relay
2026-10-22 15:19 ` [PATCH v2 10/10] docs: iio: ad9910: document DRCTL pin control Rodrigo Alencar via B4 Relay
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