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Wed, 21 Oct 2026 19:58:58 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36740cc8c6dsm13029572eec.12.2026.10.21.19.58.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 19:58:58 -0700 (PDT) From: Coia Prant To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Lin , David Heidelberg , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Coia Prant Subject: [PATCH v11 1/3] arm64: dts: rockchip: rk3568: add XPCS and fixed-clock nodes Date: Thu, 22 Oct 2026 10:58:42 +0800 Message-ID: <20261022025844.150320-2-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261022025844.150320-1-coiaprant@gmail.com> References: <20261022025844.150320-1-coiaprant@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The RK3568 SoC integrates a Synopsys DesignWare XPCS that provides the Physical Coding Sublayer for 1000BASE-X, SGMII, and QSGMII interfaces via its four MII ports. Add the XPCS device node to the SoC device tree. The XPCS device is accessed via the APB3 bus at 0xfda00000 and requires the CSR clock (PCLK_XPCS) for register access and the EEE clock (CLK_XPCS_EEE) for Energy Efficient Ethernet operation. The PD_PIPE power domain must be enabled before any register access. Also add two fixed-clock nodes (clock-xpcs-gmac0 and clock-xpcs-gmac1, labelled clk_gmac0_xpcs_mii and clk_gmac1_xpcs_mii) providing the 125 MHz reference clock for the GMACs when operating with XPCS. Their clock-output-names match the CRU mux parent names in clk-rk3568.c, so boards can reparent SCLK_GMAC0_RX_TX / SCLK_GMAC1_RX_TX through assigned-clock-parents. The XPCS node is disabled by default and must be enabled at the board level when 1000BASE-X/SGMII/QSGMII is in use. The fixed-clock nodes are always present and do not have a status property, as they are static clock sources. The XPCS node requires a reference to the appropriate Naneng Combo PHY via the phys property. dtbs_check only validates required properties for enabled nodes, so the SoC dtsi does not provide phys: boards that enable the XPCS must supply it, since the SerDes link is a board-level design choice (combphy1 on some boards, combphy2 on others). Signed-off-by: Coia Prant --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 3bc653f027f1f..20a72785adbc2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -8,6 +8,20 @@ / { compatible = "rockchip,rk3568"; + clk_gmac0_xpcs_mii: clock-xpcs-gmac0 { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clk_gmac0_xpcs_mii"; + #clock-cells = <0>; + }; + + clk_gmac1_xpcs_mii: clock-xpcs-gmac1 { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clk_gmac1_xpcs_mii"; + #clock-cells = <0>; + }; + cpu0_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -110,6 +124,15 @@ sata0: sata@fc000000 { status = "disabled"; }; + xpcs: ethernet-pcs@fda00000 { + compatible = "rockchip,rk3568-xpcs"; + reg = <0x0 0xfda00000 0x0 0x200000>; + clocks = <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>; + clock-names = "csr", "eee"; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + pipe_phy_grf0: syscon@fdc70000 { compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; reg = <0x0 0xfdc70000 0x0 0x1000>; -- 2.47.3