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Wed, 21 Oct 2026 19:59:08 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36740cc8c6dsm13029572eec.12.2026.10.21.19.59.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 19:59:08 -0700 (PDT) From: Coia Prant To: Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Lin , David Heidelberg , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Coia Prant Subject: [PATCH v11 3/3] arm64: dts: rockchip: rk3568-photonicat: enable SGMII LAN port Date: Thu, 22 Oct 2026 10:58:44 +0800 Message-ID: <20261022025844.150320-4-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261022025844.150320-1-coiaprant@gmail.com> References: <20261022025844.150320-1-coiaprant@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Ariaboard Photonicat has a Motorcomm YT8521SC Gigabit Ethernet PHY connected to GMAC0 via XPCS SGMII. Enable the necessary nodes to make this port functional. Enable the xpcs node, referencing combphy2 as the SerDes PHY. The rockchip,sgmii-mac-sel property on combphy2 is not set here. The property is tri-state: when absent, the driver leaves the routing unchanged. If the bootloader has already routed combphy2 SGMII to GMAC0, the link works without the explicit property. A follow-up will add rockchip,sgmii-mac-sel = <0> once the PHY binding lands in linux-next, removing the dependency on the bootloader default. RK3568 has three Combo PHYs that can carry SGMII; which one is wired to the XPCS is a board-level choice, and Photonicat uses combphy2. Add the mdio0 node with the YT8521SC PHY at address 3, including its reset GPIO and LED configuration. Signed-off-by: Coia Prant --- .../boot/dts/rockchip/rk3568-photonicat.dts | 48 ++++++++++++++++++- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts index 12ae9159bea87..d9015dbfb9f5c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts @@ -261,9 +261,18 @@ &cpu3 { cpu-supply = <&vdd_cpu>; }; -/* Motorcomm YT8521SC LAN port (require SGMII) */ +/* Motorcomm YT8521SC LAN port */ &gmac0 { - status = "disabled"; + assigned-clocks = <&cru SCLK_GMAC0_RX_TX>; + assigned-clock-parents = <&clk_gmac0_xpcs_mii>; + managed = "in-band-status"; + pcs-handle = <&xpcs>; + phy-handle = <&sgmii_phy>; + phy-mode = "sgmii"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_miim>; + status = "okay"; }; /* Motorcomm YT8521SC WAN port */ @@ -342,6 +351,36 @@ &i2s0_8ch { status = "okay"; }; +&mdio0 { + sgmii_phy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x3>; + max-speed = <1000>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + }; + }; +}; + &mdio1 { rgmii_phy: ethernet-phy@3 { compatible = "ethernet-phy-ieee802.3-c22"; @@ -606,3 +645,8 @@ &xin32k { pinctrl-names = "default"; pinctrl-0 = <&clk32k_out1>; }; + +&xpcs { + phys = <&combphy2 PHY_TYPE_SGMII>; + status = "okay"; +}; -- 2.47.3