From: kmahammadraf <kmahammadraf@marvell.com>
To: <linux-kernel@vger.kernel.org>, <netdev@vger.kernel.org>
Cc: Sunil Goutham <sgoutham@marvell.com>,
Ratheesh Kannoth <rkannoth@marvell.com>,
Geetha sowjanya <gakula@marvell.com>,
"Subbaraya Sundeep" <sbhatta@marvell.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@kernel.org>,
"Jakub Kicinski" <kuba@kernel.org>,
Paolo Abeni <pabeni@redhat.com>,
Satha Rao <skoteshwar@marvell.com>,
kmahammadraf <kmahammadraf@marvell.com>
Subject: [PATCH net] Subject: [PATCH] octeontx2-af: fix TX scheduler queue index mask for 2K schedulers
Date: Thu, 22 Oct 2026 04:26:53 +0000 [thread overview]
Message-ID: <20261022042653.2640537-1-kmahammadraf@marvell.com> (raw)
From: Satha Rao <skoteshwar@marvell.com>
In CN20K, the maximum number of TX schedulers per layer increased from
1K to 2K, so the scheduler queue index field is now 11 bits wide.
Update the TX scheduler masks used for mailbox/config register access:
Increase TXSCHQ_IDX_MASK from 10-bit to 11-bit
Expand NIX_TX_SCHQ_MASK to include bit 26
Signed-off-by: kmahammadraf <kmahammadraf@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
---
drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 2 +-
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index cece197d1074..1b62f9d7f00a 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -1164,7 +1164,7 @@ struct nix_txschq_config {
u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
u8 read;
#define TXSCHQ_IDX_SHIFT 16
-#define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
+#define TXSCHQ_IDX_MASK (BIT_ULL(11) - 1)
#define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
u8 num_regs;
#define MAX_REGS_PER_MBOX_MSG 20
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 95f782d47927..a1d68afd7c9e 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -2850,9 +2850,9 @@ static void nix_tl1_default_cfg(struct rvu *rvu, struct nix_hw *nix_hw,
}
/* Register offset - [15:0]
- * Scheduler Queue number - [25:16]
+ * Scheduler Queue number - [26:16]
*/
-#define NIX_TX_SCHQ_MASK GENMASK_ULL(25, 0)
+#define NIX_TX_SCHQ_MASK GENMASK_ULL(26, 0)
static int nix_txschq_cfg_read(struct rvu *rvu, struct nix_hw *nix_hw,
int blkaddr, struct nix_txschq_config *req,
--
2.25.1
next reply other threads:[~2026-10-22 4:27 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-22 4:26 kmahammadraf [this message]
2026-10-22 4:32 ` netdev-bot+sinfo
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