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Wed, 21 Oct 2026 23:46:44 -0700 (PDT) Received: from localhost.localdomain (dynamic-2a02-3100-ad43-d501-2c28-bb72-120d-420e.310.pool.telefonica.de. [2a02:3100:ad43:d501:2c28:bb72:120d:420e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e25828cd1sm10215624f8f.22.2026.10.21.23.46.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 21 Oct 2026 23:46:44 -0700 (PDT) From: Karl Mehltretter To: Marc Zyngier , Oliver Upton Cc: Karl Mehltretter , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Eric Auger , Paolo Bonzini , Sean Christopherson , Shuah Khan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH 2/3] KVM: arm64: vgic-v3: Don't drop pending writes to active level IRQs Date: Thu, 22 Oct 2026 08:46:27 +0200 Message-Id: <20261022064628.4206-3-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20261022064628.4206-1-kmehltretter@gmail.com> References: <20261022064628.4206-1-kmehltretter@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The GICv3 backend also loses a level interrupt set pending through GICD_ISPENDR or GICR_ISPENDR0 while it is active. Its LR handling has the same split between pending_latch and an Active-only LR as GICv2, and clears the new pending state after deactivation. Apply the GICv2 bookkeeping to vgic_v3_fold_lr(). Clear the old latch when the LR reports that the interrupt has been acknowledged, and preserve a latch which was not represented in the LR. GICv3 permits an implementation to clear register-set pending state on ack. Doing so matches the GICv2 backend and makes a later ISPENDR write a distinct pending state. Fixes: 67b5b673ad4d ("KVM: arm/arm64: vgic: Disallow Active+Pending for level interrupts") Assisted-by: LLM --- arch/arm64/kvm/vgic/vgic-v3.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c index 726e20a1da6e7..8009dc6df00db 100644 --- a/arch/arm64/kvm/vgic/vgic-v3.c +++ b/arch/arm64/kvm/vgic/vgic-v3.c @@ -75,7 +75,7 @@ static void vgic_v3_fold_lr(struct kvm_vcpu *vcpu, u64 val) { struct vgic_irq *irq; bool is_v2_sgi = false; - bool deactivated; + bool deactivated, was_active; u32 intid; if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { @@ -93,7 +93,8 @@ static void vgic_v3_fold_lr(struct kvm_vcpu *vcpu, u64 val) /* Always preserve the active bit for !LPIs, note deactivation */ if (irq->intid >= VGIC_MIN_LPI) val &= ~ICH_LR_ACTIVE_BIT; - deactivated = irq->active && !(val & ICH_LR_ACTIVE_BIT); + was_active = irq->active; + deactivated = was_active && !(val & ICH_LR_ACTIVE_BIT); irq->active = !!(val & ICH_LR_ACTIVE_BIT); /* Edge is the only case where we preserve the pending bit */ @@ -103,9 +104,15 @@ static void vgic_v3_fold_lr(struct kvm_vcpu *vcpu, u64 val) /* * Clear soft pending state when level irqs have been acked. + * A latch written while the irq was active is a new pending + * state. A write while the irq was in the LR may also have + * followed the ack, so preserve it too. */ - if (irq->config == VGIC_CONFIG_LEVEL && !(val & ICH_LR_STATE)) + if (irq->config == VGIC_CONFIG_LEVEL && + !(val & ICH_LR_PENDING_BIT) && + !was_active && !irq->latch_written) irq->pending_latch = false; + irq->latch_written = false; if (is_v2_sgi) { u8 cpuid = FIELD_GET(GICH_LR_PHYSID_CPUID, val); -- 2.39.5 (Apple Git-154)