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This series has been tested on the JHB100 SoC. # cat /sys/kernel/debug/spi-nor/spi0.1/capabilities Supported read modes by the flash [...] 1S-4D-4D opcode 0xee mode cycles 0 dummy cycles 6 Changhuang Liang (4): spi: dw: Add DDR (Dual Data-Rate) support for enhanced SPI mode mtd: spi-nor: Support mixed 1S-xD-xD DTR protocols in spi_nor_spimem_setup_op() mtd: spi-nor: debugfs: Correct DTR protocol names for 1S-xD-xD modes mtd: spi-nor: macronix: Add 1-4-4 DTR read support for MX66L1G45G drivers/mtd/spi-nor/core.c | 21 +++++++++----- drivers/mtd/spi-nor/debugfs.c | 8 +++--- drivers/mtd/spi-nor/macronix.c | 28 +++++++++++++++++- drivers/spi/spi-dw-core.c | 52 +++++++++++++++++++++++++++++----- drivers/spi/spi-dw.h | 6 ++++ 5 files changed, 96 insertions(+), 19 deletions(-) -- 2.25.1