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mx.microsoft.com 1; spf=pass smtp.mailfrom=starfivetech.com; dmarc=pass action=none header.from=starfivetech.com; dkim=pass header.d=starfivetech.com; arc=none Authentication-Results: mx.microsoft.com 1; dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=starfivetech.com; Received: from ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (10.2.3.102) by ZQ4PR01MB1298.CHNPR01.prod.partner.outlook.cn (10.2.3.110) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.546.16; Thu, 22 Oct 2026 10:26:23 +0000 Received: from ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn ([fe80::e7d4:256c:b066:850d]) by ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn ([fe80::e7d4:256c:b066:850d%4]) with mapi id 15.21.0546.016; Thu, 22 Oct 2026 10:26:23 +0000 From: Changhuang Liang To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Mark Brown , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org, Changhuang Liang Subject: [PATCH v1 2/4] mtd: spi-nor: Support mixed 1S-xD-xD DTR protocols in spi_nor_spimem_setup_op() Date: Thu, 22 Oct 2026 03:26:12 -0700 Message-Id: <20261022102614.75696-3-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20261022102614.75696-1-changhuang.liang@starfivetech.com> References: <20261022102614.75696-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: ZQ0PR01CA0009.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:5::23) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1298:EE_ X-MS-Office365-Filtering-Correlation-Id: 28e6eb09-1a85-4d91-778f-08df3026ec00 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|7416014|376014|23010399003|52116014|1800799024|22082099003|18002099003|3023799007|38350700014|261009223027099003|10067099003|261021123027099003|261021121427099003|56012099006; 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This is too coarse: the 1S-xD-xD DTR protocols (1_1_1_DTR, 1_2_2_DTR, 1_4_4_DTR, 1_8_8_DTR) send the command phase in STR on a single line, and only the address, dummy and data phases in DTR. SPIMEM supports such mixed DTR modes. Split the handling: - For SNOR_PROTO_8_8_8_DTR, keep the existing behavior: set all phases to DTR and use a 2-byte opcode (opcode + extension). - For the other DTR protocols, set the command phase to STR and only the address, dummy and data phases to DTR. Double op->dummy.nbytes since DTR transfers 2 bytes per clock cycle, matching how the dummy cycle count is specified for these protocols. No in-tree flash currently declares SNOR_HWCAPS_READ_1_x_x_DTR, so this is not a bug fix but preparation for enabling these protocols. A follow-up patch will enable 1S-4D-4D for the MX66L1G45G. The 8D-8D-8D path is unchanged. Signed-off-by: Changhuang Liang --- drivers/mtd/spi-nor/core.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 90524c58602e..43e506e728ab 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -97,13 +97,7 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, if (op->data.nbytes) op->data.buswidth = spi_nor_get_protocol_data_nbits(proto); - if (spi_nor_protocol_is_dtr(proto)) { - /* - * SPIMEM supports mixed DTR modes, but right now we can only - * have all phases either DTR or STR. IOW, SPIMEM can have - * something like 4S-4D-4D, but SPI NOR can't. So, set all 4 - * phases to either DTR or STR. - */ + if (proto == SNOR_PROTO_8_8_8_DTR) { op->cmd.dtr = true; op->addr.dtr = true; op->dummy.dtr = true; @@ -115,6 +109,19 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, ext = spi_nor_get_cmd_ext(nor, op); op->cmd.opcode = (op->cmd.opcode << 8) | ext; op->cmd.nbytes = 2; + } else if (spi_nor_protocol_is_dtr(proto)) { + /* + * 1S-xD-xD protocols: the opcode is sent in STR on a single + * line, only the address, dummy and data phases are DTR. The + * opcode stays 1 byte (no command extension). + */ + op->cmd.dtr = false; + op->addr.dtr = true; + op->dummy.dtr = true; + op->data.dtr = true; + + /* 2 bytes per clock cycle in DTR mode. */ + op->dummy.nbytes *= 2; } if (proto == SNOR_PROTO_8_8_8_DTR && params->flags & SNOR_F_SWAP16) -- 2.25.1