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Thu, 22 Oct 2026 04:48:12 -0700 (PDT) Received: from localhost.localdomain ([177.155.254.104]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-990d117c005sm6177793241.9.2026.10.22.04.48.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2026 04:48:12 -0700 (PDT) From: Matheus Tagliari To: Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , =?UTF-8?q?Timur=20Krist=C3=B3f?= Cc: Matheus Tagliari , David Airlie , Simona Vetter , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/2] drm/radeon: fix VCE1 encoding on SI by handling the VCE interrupt Date: Thu, 22 Oct 2026 08:47:45 -0300 Message-ID: <20261022114754.865669-1-mptagliari@gmail.com> X-Mailer: git-send-email 2.47.3 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hardware H.264 encoding with the VCE block on SI GPUs (radeon driver) hangs the GPU after a few dozen frames. I hit it with the KDE Plasma RDP server, which encodes through VAAPI, and reproduced it with a plain "ffmpeg -vaapi_device ... -c:v h264_vaapi" test on a Radeon HD 8870M (Cape Verde). The VCE1 code never enables the VCE trap interrupt and the SI (and Trinity) interrupt handlers do not process it, unlike the CIK code and amdgpu. Patch 1 adds the handlers, patch 2 enables the interrupt. Results on Debian 6.12.113 (see patch 2 for numbers): hang before, none after, and 34 fps instead of ~4 fps for the workaround that avoids the hang. The KDE RDP server (KRDP) itself, driven by a local FreeRDP client, now encodes on the VCE ring for several minutes (about 40 fences per second on ring 6 in the radeon_fence_emit tracepoint) with a clean kernel log. Two caveats: - I have not worked out why the missing interrupt turns into ring lockups instead of only added latency. What I know is that the hang needs the VCE ring to wait on a hardware semaphore (disabling only the waiting side, or both sides, of radeon_vce_semaphore_emit() avoids it) and that handling the interrupt makes it go away with the semaphores left enabled. If someone knows why, I would be glad to improve the commit message. - The Trinity/Richland change has not been tested on that hardware. The series was developed and tested on Debian's 6.12.113 with the radeon module built out of tree. It applies cleanly on drm-next (fad06cf), where drivers/gpu/drm/radeon builds without warnings (W=1, allmodconfig) both after patch 1 and with the whole series. v1: https://lore.kernel.org/r/20261021114122.94008-1-mptagliari@gmail.com Changes in v2: - Patch 2: only enable VCE_SYS_INT_EN for VCE1 (family < CHIP_BONAIRE). vce_v1_0_start() is also reached on CIK (vce_v1_0_init() from cik.c, kv_dpm), where the register is at a different offset and is already enabled by vce_v2_0_resume(); v1 would have written the VCE1 offset there. Thanks to the automated review of v1 for pointing this out. - Patch 1: unchanged. Matheus Tagliari (2): drm/radeon: process the VCE interrupt on SI and Trinity drm/radeon/vce1: enable the VCE trap interrupt drivers/gpu/drm/radeon/evergreen.c | 14 ++++++++++++++ drivers/gpu/drm/radeon/si.c | 14 ++++++++++++++ drivers/gpu/drm/radeon/sid.h | 2 ++ drivers/gpu/drm/radeon/vce_v1_0.c | 9 +++++++++ 4 files changed, 39 insertions(+) base-commit: fad06cfaf385787b9ffa2f73f049d42dbe1de57f -- 2.47.3