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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CY7PEPF000000F5.mail.protection.outlook.com (10.167.247.153) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.546.15 via Frontend Transport; Thu, 22 Oct 2026 14:08:31 +0000 Received: from BLR-L1-SARUNKOD.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.53; Thu, 22 Oct 2026 09:08:20 -0500 From: Sairaj Kodilkar To: "H. Peter Anvin" , "Joerg Roedel (AMD)" , "Mike Rapoport (Microsoft)" , Andrew Morton , Borislav Petkov , Dapeng Mi , Dave Hansen , Ethan Nelson-Moore , Ingo Molnar , Jakub Kicinski , Jeff Layton , "Jonathan Corbet" , Kiryl Shutsemau , Li RongQing , Marco Elver , Paolo Bonzini , Randy Dunlap , Rick Edgecombe , Robin Murphy , "Sairaj Kodilkar" , Sean Christopherson , "Shuah Khan" , Suravee Suthikulpanit , Thomas Gleixner , "Vasant Hegde" , Will Deacon , , , , , , Subject: [PATCH v6 4/7] iommu/amd: Program guest-mode IRTEs for GAPPI wakeup when IRTE[IsRun] = 0 Date: Thu, 22 Oct 2026 19:34:22 +0530 Message-ID: <20261022140425.27465-5-sarunkod@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261022140425.27465-1-sarunkod@amd.com> References: <20261022140425.27465-1-sarunkod@amd.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY7PEPF000000F5:EE_|DS4PR12MB9658:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d4ef04d-391b-46ee-3ec7-08df3045f3e3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|1800799024|82310400026|7416014|376014|36860700016|13003099007|921020|11063799006|56012099006|261021123027099003|261021121427099003|261009223027099003|10067099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: zJY5YUWcOcsemp5V5DnxgGqY7DpEC2BCjOkdsvTWsjz7pxIsrkOcgy0stg4qd71kF41LJakGeCF8BgJ81XAS5VnpM2y1+AOrk9UJ2bBnkOBhDQkYLMDAACRpd/T700Vc1MxY4pYvW27FeFJk7XEHcmRFIoj5xGv8/QADlpzY2d3Pu6E2uz2aVGmKkHeprVHshG1ggj+HKMu9PkRpeZh0eXaVh5+DxFgyijsBwPYoJjQBb5CPE3IyrICUs+wh+AgqscF2T/uLqEa3ebavVTd0Ak39sjWlNLPdQ9Pqc+6elh1kiHP4gEA6gE8l30ZP4pHvP1ZE0C1oqITr/XP2vLFd5e8WBJ5dUzOCNtinxx69wuK5cXAGNdTZ7VpAdu9sXZQQHqc9r5Gj6FxSDv6pm+07o1n4X5h02jkFnzbyab8pVQQGSkhuVtmxo6os2wKQts055UpjV1N3nGJMYGJYmdcNe0WpbYlj4gzI0CzYmuDVG3x88OceFVTV35BTSdA02wNYrkIecs30pKu+PbKLsIfwVWrEILF/VRCE6oisF4UiNzKGko1xjgabfPhvYrtrceCZxWv1lLz2TKr0RlzY8INBWbkTrwm+qqecBllA1flh0PGZfmVSOBfZIuK//PKcmZMOHNXyROtyh+V34eruY/lZP7wN9J3PtPbEpqk3eQn0B3dRK3WrXkLSF1fC+X8eWx6UDfGpx3jidvkf7D0QE0vwxVb/BA3o2rVFbNwRKvqXLYvHqKVCOnHfDgzXgr14IJ83 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(23010399003)(1800799024)(82310400026)(7416014)(376014)(36860700016)(13003099007)(921020)(11063799006)(56012099006)(261021123027099003)(261021121427099003)(261009223027099003)(10067099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: HvrE56+RamiNz4ZmgbX4/qnPTRh2PTqXaAGLhRU3ZqURMNVj9yGkVbjS9SSyGpb+Dv2t9T6YVxOdLxem/SYhxBMKm9q0kBXDb6OblSyvPZZYlwm8QeJnWBHWgTPksrbLM5UQC1hsVY8KSg4PO3abdEtbbV3ySTa7aO7KG+uWy5wbYbYMJu7o+/abAvbA7mVTDocFsFO5n/efEezQQkNA/Co1YCclgIO8QJGSegeAX+s3KoI/MtC3+s0mxsxaLSYBEdYtLSuYmE+M3b9dHg50fbflkILaU5kw/EFY8doqM7mIBHmkR99HQF6oRtsTbPj2dqKOjFbw0DR85/YzGJj0KQT4LzeXbyr+rPUyvEIUiRsNcu4cuWC2ucVIqs+JOyeAx+5+JK48//imCKL+F3FIEewh3C09ZMMK4GwSmxtezVouAuAmK7TZkg3htlyHpIdu X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2026 14:08:31.1681 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d4ef04d-391b-46ee-3ec7-08df3045f3e3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY7PEPF000000F5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9658 Guest APIC Physical Processor Interrupt (GAPPI) is an alternative to the GA log for notifying the host when a device interrupt targets a non-running vCPU (IRTE[IsRun] = 0). Per the AMD IOMMU specification [1] (section 2.2.5.4), with GAPPI enabled the IOMMU delivers a physical APIC interrupt to the CPU described by IRTE[Destination], using IRTE[GATag][7:0] as the vector, while still updating the guest vAPIC backing page IRR as usual. The AMD IOMMU also allows suppressing GAPPI interrupts using the IRTE[GAPPIDis] bit when the GAPPIDisSup feature is available in extended feature register 2. The AMD IOMMU driver sets this bit when the wakeup_intr flag is not set by KVM. Note: amd_iommu_gappi is currently false; a later patch enables it via the kernel command line. [1] https://docs.amd.com/v/u/en-US/48882_3.11_IOMMU_PUB Signed-off-by: Sairaj Kodilkar Reviewed-by: Vasant Hegde --- drivers/iommu/amd/amd_iommu_types.h | 4 +++- drivers/iommu/amd/init.c | 5 +++++ drivers/iommu/amd/iommu.c | 31 +++++++++++++++++++---------- include/linux/amd-iommu.h | 6 ++++++ 4 files changed, 35 insertions(+), 11 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 8241ef922519..b89a2b3df0a4 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -97,6 +97,7 @@ /* Extended Feature 2 Bits */ #define FEATURE_SEVSNPIO_SUP BIT_ULL(1) #define FEATURE_GCR3TRPMODE BIT_ULL(3) +#define FEATURE_GAPPIDISSUP BIT_ULL(4) #define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5) #define FEATURE_SNPAVICSUP_GAM(x) \ (FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1) @@ -982,7 +983,8 @@ union irte_ga_lo { no_fault : 1, /* ------ */ ga_log_intr : 1, - rsvd1 : 3, + rsvd1 : 2, + gappi_dis : 1, is_run : 1, /* ------ */ guest_mode : 1, diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 8a410d4aa370..78e3c14dc1c2 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -160,6 +160,11 @@ u8 amd_iommu_hpt_vasize; /* Guest page table level */ int amd_iommu_gpt_level = PAGE_MODE_4_LEVEL; +#ifdef CONFIG_IRQ_REMAP +bool amd_iommu_gappi; +EXPORT_SYMBOL(amd_iommu_gappi); +#endif + int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC; static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE; diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 099df57384e9..5bf4621d9be5 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -4003,9 +4003,20 @@ static void __amd_iommu_update_ga(struct irte_ga *entry, int apicid, APICID_TO_IRTE_DEST_HI(apicid); entry->lo.fields_vapic.is_run = true; entry->lo.fields_vapic.ga_log_intr = false; + entry->lo.fields_vapic.gappi_dis = false; } else { - entry->lo.fields_vapic.is_run = false; - entry->lo.fields_vapic.ga_log_intr = wakeup_intr; + if (amd_iommu_gappi) { + entry->lo.fields_vapic.gappi_dis = !wakeup_intr && + check_feature2(FEATURE_GAPPIDISSUP); + entry->lo.fields_vapic.is_run = false; + entry->lo.fields_vapic.destination = + APICID_TO_IRTE_DEST_LO(apicid); + entry->hi.fields.destination = + APICID_TO_IRTE_DEST_HI(apicid); + } else { + entry->lo.fields_vapic.is_run = false; + entry->lo.fields_vapic.ga_log_intr = wakeup_intr; + } } } @@ -4016,15 +4027,15 @@ static void __amd_iommu_update_ga(struct irte_ga *entry, int apicid, * If the vCPU is scheduled to run on pCPU (@is_running = 1), configure the * Destination with the pCPU's APIC ID, set IsRun, and clear GALogIntr. If the * vCPU is scheduled out (@is_running = 0), clear IsRun and set/clear GALogIntr - * based on input from the caller (e.g. KVM only requests wakeup_intr when the - * vCPU is blocking and requires a notification wake event). This API is - * intended to be used when a vCPU is scheduled in/out (or stops running for - * any reason), to do a fast update of IsRun, GALogIntr, and (conditionally) - * Destination. + * and GAPPIDis based on input from the caller (e.g. KVM only requests + * wakeup_intr when the vCPU is blocking and requires a notification wake + * event). This API is intended to be used when a vCPU is scheduled in/out (or + * stops running for any reason), to do a fast update of IsRun, GALogIntr, + * GAPPIDis and (conditionally) Destination. * - * Per the IOMMU spec, the Destination, IsRun, and GATag fields are not cached - * and thus don't require an invalidation to ensure the IOMMU consumes fresh - * information. + * Per the IOMMU spec, the Destination, IsRun, GATag and GAPPIDis fields are + * not cached and thus don't require an invalidation to ensure the IOMMU + * consumes fresh information. */ int amd_iommu_update_ga(void *data, int apicid, bool wakeup_intr, bool is_running) { diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h index e07dc8efac32..68a42427fdf9 100644 --- a/include/linux/amd-iommu.h +++ b/include/linux/amd-iommu.h @@ -35,6 +35,9 @@ extern int amd_iommu_update_ga(void *data, int apicid, bool wakeup_intr, extern int amd_iommu_activate_guest_mode(void *data, int apicid); extern int amd_iommu_deactivate_guest_mode(void *data); +/* IOMMU AVIC Flag */ +extern bool amd_iommu_gappi; + #else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */ static inline int @@ -58,6 +61,9 @@ static inline int amd_iommu_deactivate_guest_mode(void *data) { return 0; } + +#define amd_iommu_gappi false + #endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */ int amd_iommu_get_num_iommus(void); -- 2.34.1