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From: Andrew Jones <andrew.jones@linux.dev>
To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev
Cc: linux-kernel@vger.kernel.org, tomasz.jeznach@linux.dev,
	jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org,
	robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
	anup@brainfault.org, tglx@kernel.org, kevin.tian@intel.com,
	fangyu.yu@linux.alibaba.com, nutty.liu@hotmail.com
Subject: [PATCH v7 1/5] iommu/dma: Prepare MSI physical address lists
Date: Thu, 22 Oct 2026 17:45:59 +0200	[thread overview]
Message-ID: <20261022154603.1374754-2-andrew.jones@linux.dev> (raw)
In-Reply-To: <20261022154603.1374754-1-andrew.jones@linux.dev>

IMSIC affinity changes need every possible target mapped. Introduce
iommu_dma_sw_msi_list() to cache one contiguous IOVA range base for
a list of targets.

Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
Signed-off-by: Andrew Jones <andrew.jones@linux.dev>
---
 drivers/iommu/dma-iommu.c | 77 +++++++++++++++++++++++++++++++++++----
 drivers/iommu/dma-iommu.h | 10 +++++
 2 files changed, 80 insertions(+), 7 deletions(-)

diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index 1f624f241ac1..1046b19be584 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -59,6 +59,8 @@ struct iommu_dma_options {
 struct iommu_dma_cookie {
 	struct iova_domain iovad;
 	struct list_head msi_page_list;
+	/* Base IOVA of the complete MSI target list */
+	dma_addr_t msi_list_iova;
 	/* Flush queue */
 	union {
 		struct iova_fq *single_fq;
@@ -2204,13 +2206,42 @@ static struct list_head *cookie_msi_pages(const struct iommu_domain *domain)
 	}
 }
 
+static dma_addr_t iommu_dma_alloc_msi_iova(struct device *dev, struct iommu_domain *domain,
+					   const phys_addr_t *phys_addrs,
+					   unsigned int nr_addrs, size_t granule)
+{
+	int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
+	size_t size = nr_addrs * granule;
+	dma_addr_t iova;
+	unsigned int i;
+
+	iova = iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev);
+	if (!iova)
+		return 0;
+
+	for (i = 0; i < nr_addrs; i++) {
+		if (iommu_map(domain, iova + i * granule, phys_addrs[i], granule,
+			      prot, GFP_KERNEL))
+			goto out_unmap;
+	}
+	return iova;
+
+out_unmap:
+	if (i) {
+		size_t mapped = i * granule;
+
+		WARN_ON_ONCE(iommu_unmap(domain, iova, mapped) != mapped);
+	}
+	iommu_dma_free_iova(domain, iova, size, NULL);
+	return 0;
+}
+
 static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev,
 		phys_addr_t msi_addr, struct iommu_domain *domain)
 {
 	struct list_head *msi_page_list = cookie_msi_pages(domain);
 	struct iommu_dma_msi_page *msi_page;
 	dma_addr_t iova;
-	int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
 	size_t size = cookie_msi_granule(domain);
 	static DEFINE_MUTEX(msi_prepare_lock);
 
@@ -2235,21 +2266,16 @@ static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev,
 	if (!msi_page)
 		return NULL;
 
-	iova = iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev);
+	iova = iommu_dma_alloc_msi_iova(dev, domain, &msi_addr, 1, size);
 	if (!iova)
 		goto out_free_page;
 
-	if (iommu_map(domain, iova, msi_addr, size, prot, GFP_KERNEL))
-		goto out_free_iova;
-
 	INIT_LIST_HEAD(&msi_page->list);
 	msi_page->phys = msi_addr;
 	msi_page->iova = iova;
 	list_add(&msi_page->list, msi_page_list);
 	return msi_page;
 
-out_free_iova:
-	iommu_dma_free_iova(domain, iova, size, NULL);
 out_free_page:
 	kfree(msi_page);
 	return NULL;
@@ -2271,6 +2297,43 @@ int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc,
 	return 0;
 }
 
+/*
+ * All calls for a DMA domain must supply the same complete target list.
+ * The group mutex serializes creation and reuse of the cached mapping.
+ */
+int iommu_dma_sw_msi_list(struct iommu_domain *domain, struct msi_desc *desc,
+			  const phys_addr_t *phys_addrs, unsigned int nr_addrs,
+			  size_t granule)
+{
+	struct device *dev = msi_desc_to_dev(desc);
+	struct iommu_dma_cookie *cookie;
+	unsigned int i;
+
+	iommu_group_mutex_assert(dev);
+	if (domain->cookie_type != IOMMU_COOKIE_DMA_IOVA)
+		return -EOPNOTSUPP;
+
+	cookie = domain->iova_cookie;
+	if (granule < PAGE_SIZE || granule != cookie->iovad.granule)
+		return -EOPNOTSUPP;
+	if (!nr_addrs || nr_addrs > SIZE_MAX / granule)
+		return -EINVAL;
+
+	if (!cookie->msi_list_iova) {
+		for (i = 0; i < nr_addrs; i++)
+			if (!IS_ALIGNED(phys_addrs[i], granule))
+				return -EINVAL;
+
+		cookie->msi_list_iova = iommu_dma_alloc_msi_iova(dev, domain, phys_addrs,
+								 nr_addrs, granule);
+		if (!cookie->msi_list_iova)
+			return -ENOMEM;
+	}
+
+	msi_desc_set_iommu_msi_iova(desc, cookie->msi_list_iova, ilog2(granule));
+	return 0;
+}
+
 static int iommu_dma_init(void)
 {
 	if (is_kdump_kernel())
diff --git a/drivers/iommu/dma-iommu.h b/drivers/iommu/dma-iommu.h
index 040d00252563..2a36ed736910 100644
--- a/drivers/iommu/dma-iommu.h
+++ b/drivers/iommu/dma-iommu.h
@@ -21,6 +21,9 @@ void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list);
 
 int iommu_dma_sw_msi(struct iommu_domain *domain, struct msi_desc *desc,
 		     phys_addr_t msi_addr);
+int iommu_dma_sw_msi_list(struct iommu_domain *domain, struct msi_desc *desc,
+			  const phys_addr_t *phys_addrs, unsigned int nr_addrs,
+			  size_t granule);
 
 extern bool iommu_dma_forcedac;
 
@@ -59,5 +62,12 @@ static inline int iommu_dma_sw_msi(struct iommu_domain *domain,
 	return -ENODEV;
 }
 
+static inline int iommu_dma_sw_msi_list(struct iommu_domain *domain, struct msi_desc *desc,
+					const phys_addr_t *phys_addrs, unsigned int nr_addrs,
+					size_t granule)
+{
+	return -ENODEV;
+}
+
 #endif	/* CONFIG_IOMMU_DMA */
 #endif	/* __DMA_IOMMU_H */
-- 
2.56.0


  reply	other threads:[~2026-10-22 15:46 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-22 15:45 [PATCH v7 0/5] iommu/riscv: Enable MSI remapping and IOMMU_DMA Andrew Jones
2026-10-22 15:45 ` Andrew Jones [this message]
2026-10-22 15:46 ` [PATCH v7 2/5] iommu/dma: Introduce iommu_dma_prepare_msi_list() Andrew Jones
2026-10-22 15:46 ` [PATCH v7 3/5] irqchip/riscv-imsic: Add MSI address list Andrew Jones
2026-10-22 15:46 ` [PATCH v7 4/5] irqchip/riscv-imsic: Support IOMMU MSI address lists Andrew Jones
2026-10-22 15:46 ` [PATCH v7 5/5] iommu/dma: Enable IOMMU_DMA for 64-bit RISC-V Andrew Jones

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