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Thu, 22 Oct 2026 09:31:09 -0700 (PDT) Received: from eldorado ([2600:8802:b00:1f88::287]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3674198e2d6sm15771540eec.22.2026.10.22.09.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2026 09:31:08 -0700 (PDT) From: Florian Fainelli To: linux-mips@vger.kernel.org Cc: macro@orcam.me.uk, Florian Fainelli , Thomas Bogendoerfer , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , Bjorn Helgaas , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2] MIPS: Cobalt: Include legacy IDE ports in the PCI I/O window Date: Thu, 22 Oct 2026 09:31:00 -0700 Message-ID: <20261022163106.1410595-1-f.fainelli@gmail.com> X-Mailer: git-send-email 2.53.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The Cobalt PCI I/O window starts at 0x1000, excluding the VIA IDE controller's fixed compatibility-mode ports at 0x170, 0x1f0, 0x376 and 0x3f6. Since pcibios_enable_device() was converted to pci_enable_resources(), these unclaimed resources cause pata_via to fail to probe with -EINVAL. Start the PCI I/O window at zero to cover the southbridge legacy ports, retaining 0x1000 as the allocation minimum via PCIBIOS_MIN_IO. Register the PCI controller from plat_mem_setup(), before the VIA reservations and i8259 initialization, so the legacy resources do not conflict with the host bridge window and prevent PCI bus scanning. Keep the VIA resource reservations in plat_mem_setup() after the PCI controller registration and use insert_resource() to nest them beneath the PCI window. The i8259 and RTC resources are also claimed beneath it. Boot-tested on a Qube2 with a MIPS64 kernel. All seven PCI functions enumerate, both tulip devices bind, and pata_via initializes both ATA hosts and detects the ST380012A 80 GB disk. All 18 boot checks pass, including a read-only disk test and Ethernet ping. Fixes: ae81aad5c2e1 ("MIPS: PCI: Use pci_enable_resources()") Signed-off-by: Florian Fainelli --- Changes in v2: - implement Maciej's suggestion to reserve PCI resources first and then the rest of the peripherals arch/mips/cobalt/pci.c | 11 +++++------ arch/mips/cobalt/setup.c | 4 +++- arch/mips/include/asm/mach-cobalt/cobalt.h | 1 + 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/arch/mips/cobalt/pci.c b/arch/mips/cobalt/pci.c index 85ec9cc31d66..29fd052766b2 100644 --- a/arch/mips/cobalt/pci.c +++ b/arch/mips/cobalt/pci.c @@ -14,6 +14,8 @@ #include +#include + extern struct pci_ops gt64xxx_pci0_ops; static struct resource cobalt_mem_resource = { @@ -24,7 +26,7 @@ static struct resource cobalt_mem_resource = { }; static struct resource cobalt_io_resource = { - .start = 0x1000, + .start = 0, .end = 0xffffffUL, .name = "PCI I/O", .flags = IORESOURCE_IO, @@ -38,11 +40,8 @@ static struct pci_controller cobalt_pci_controller = { .io_map_base = CKSEG1ADDR(GT_DEF_PCI0_IO_BASE), }; -static int __init cobalt_pci_init(void) +void __init cobalt_pci_init(void) { + PCIBIOS_MIN_IO = 0x1000; register_pci_controller(&cobalt_pci_controller); - - return 0; } - -arch_initcall(cobalt_pci_init); diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index 9a266bf78339..502acc92969b 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -83,9 +83,11 @@ void __init plat_mem_setup(void) /* I/O port resource */ ioport_resource.end = 0x01ffffff; + cobalt_pci_init(); + /* These resources have been reserved by VIA SuperI/O chip. */ for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++) - request_resource(&ioport_resource, cobalt_reserved_resources + i); + insert_resource(&ioport_resource, cobalt_reserved_resources + i); } /* diff --git a/arch/mips/include/asm/mach-cobalt/cobalt.h b/arch/mips/include/asm/mach-cobalt/cobalt.h index 97f9d5e9446d..c7a8607cd651 100644 --- a/arch/mips/include/asm/mach-cobalt/cobalt.h +++ b/arch/mips/include/asm/mach-cobalt/cobalt.h @@ -19,6 +19,7 @@ extern int cobalt_board_id; #define COBALT_BRD_ID_QUBE2 0x5 #define COBALT_BRD_ID_RAQ2 0x6 +void cobalt_pci_init(void); void cobalt_machine_halt(void); void cobalt_machine_restart(char *command); -- 2.53.0